From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Kzri9-0007HT-LB for qemu-devel@nongnu.org; Tue, 11 Nov 2008 06:47:09 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Kzri8-0007H0-Qw for qemu-devel@nongnu.org; Tue, 11 Nov 2008 06:47:09 -0500 Received: from [199.232.76.173] (port=38228 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Kzri8-0007Gt-K2 for qemu-devel@nongnu.org; Tue, 11 Nov 2008 06:47:08 -0500 Received: from savannah.gnu.org ([199.232.41.3]:33274 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Kzri8-0007mt-5P for qemu-devel@nongnu.org; Tue, 11 Nov 2008 06:47:08 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1Kzri7-0003ms-Hx for qemu-devel@nongnu.org; Tue, 11 Nov 2008 11:47:07 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1Kzri7-0003mo-9A for qemu-devel@nongnu.org; Tue, 11 Nov 2008 11:47:07 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Tue, 11 Nov 2008 11:47:07 +0000 Subject: [Qemu-devel] [5679] target-mips: convert bit shuffle ops to TCG Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5679 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5679 Author: aurel32 Date: 2008-11-11 11:47:06 +0000 (Tue, 11 Nov 2008) Log Message: ----------- target-mips: convert bit shuffle ops to TCG Bit shuffle operations can be written with very few TCG instructions (between 5 and 8), so it is worth converting them to TCG. This code also move all bit shuffle generation code to a separate function in order to have a cleaner exception code path, that is it doesn't store back the TCG register to the target register after the exception, as the TCG register doesn't exist anymore. Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/target-mips/helper.h trunk/target-mips/op_helper.c trunk/target-mips/translate.c Modified: trunk/target-mips/helper.h =================================================================== --- trunk/target-mips/helper.h 2008-11-11 11:46:58 UTC (rev 5678) +++ trunk/target-mips/helper.h 2008-11-11 11:47:06 UTC (rev 5679) @@ -269,10 +269,3 @@ DEF_HELPER(target_ulong, do_rdhwr_ccres, (void)) DEF_HELPER(void, do_pmon, (int function)) DEF_HELPER(void, do_wait, (void)) - -/* Bit shuffle operations. */ -DEF_HELPER(target_ulong, do_wsbh, (target_ulong t1)) -#ifdef TARGET_MIPS64 -DEF_HELPER(target_ulong, do_dsbh, (target_ulong t1)) -DEF_HELPER(target_ulong, do_dshd, (target_ulong t1)) -#endif Modified: trunk/target-mips/op_helper.c =================================================================== --- trunk/target-mips/op_helper.c 2008-11-11 11:46:58 UTC (rev 5678) +++ trunk/target-mips/op_helper.c 2008-11-11 11:47:06 UTC (rev 5679) @@ -1781,25 +1781,6 @@ return 0; } -/* Bit shuffle operations. */ -target_ulong do_wsbh(target_ulong t1) -{ - return (int32_t)(((t1 << 8) & ~0x00FF00FF) | ((t1 >> 8) & 0x00FF00FF)); -} - -#if defined(TARGET_MIPS64) -target_ulong do_dsbh(target_ulong t1) -{ - return ((t1 << 8) & ~0x00FF00FF00FF00FFULL) | ((t1 >> 8) & 0x00FF00FF00FF00FFULL); -} - -target_ulong do_dshd(target_ulong t1) -{ - t1 = ((t1 << 16) & ~0x0000FFFF0000FFFFULL) | ((t1 >> 16) & 0x0000FFFF0000FFFFULL); - return (t1 << 32) | (t1 >> 32); -} -#endif - void do_pmon (int function) { function /= 2; Modified: trunk/target-mips/translate.c =================================================================== --- trunk/target-mips/translate.c 2008-11-11 11:46:58 UTC (rev 5678) +++ trunk/target-mips/translate.c 2008-11-11 11:47:06 UTC (rev 5679) @@ -2771,6 +2771,60 @@ tcg_temp_free(t1); } +static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd) +{ + TCGv t0 = tcg_temp_new(TCG_TYPE_TL); + TCGv t1 = tcg_temp_new(TCG_TYPE_TL); + + gen_load_gpr(t1, rt); + switch (op2) { + case OPC_WSBH: + tcg_gen_shri_tl(t0, t1, 8); + tcg_gen_andi_tl(t0, t0, 0x00FF00FF); + tcg_gen_shli_tl(t1, t1, 8); + tcg_gen_andi_tl(t1, t1, ~0x00FF00FF); + tcg_gen_or_tl(t0, t0, t1); + tcg_gen_ext32s_tl(t0, t0); + break; + case OPC_SEB: + tcg_gen_ext8s_tl(t0, t1); + break; + case OPC_SEH: + tcg_gen_ext16s_tl(t0, t1); + break; +#if defined(TARGET_MIPS64) + case OPC_DSBH: + gen_load_gpr(t1, rt); + tcg_gen_shri_tl(t0, t1, 8); + tcg_gen_andi_tl(t0, t0, 0x00FF00FF00FF00FFULL); + tcg_gen_shli_tl(t1, t1, 8); + tcg_gen_andi_tl(t1, t1, ~0x00FF00FF00FF00FFULL); + tcg_gen_or_tl(t0, t0, t1); + break; + case OPC_DSHD: + gen_load_gpr(t1, rt); + tcg_gen_shri_tl(t0, t1, 16); + tcg_gen_andi_tl(t0, t0, 0x0000FFFF0000FFFFULL); + tcg_gen_shli_tl(t1, t1, 16); + tcg_gen_andi_tl(t1, t1, ~0x0000FFFF0000FFFFULL); + tcg_gen_or_tl(t1, t0, t1); + tcg_gen_shri_tl(t0, t1, 32); + tcg_gen_shli_tl(t1, t1, 32); + tcg_gen_or_tl(t0, t0, t1); + break; +#endif + default: + MIPS_INVAL("bsfhl"); + generate_exception(ctx, EXCP_RI); + tcg_temp_free(t0); + tcg_temp_free(t1); + return; + } + gen_store_gpr(t0, rd); + tcg_temp_free(t0); + tcg_temp_free(t1); +} + #ifndef CONFIG_USER_ONLY /* CP0 (MMU and control) */ static inline void gen_mfc0_load32 (TCGv t, target_ulong off) @@ -7953,34 +8007,7 @@ case OPC_BSHFL: check_insn(env, ctx, ISA_MIPS32R2); op2 = MASK_BSHFL(ctx->opcode); - { - TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL); - TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL); - - switch (op2) { - case OPC_WSBH: - gen_load_gpr(t1, rt); - tcg_gen_helper_1_1(do_wsbh, t0, t1); - gen_store_gpr(t0, rd); - break; - case OPC_SEB: - gen_load_gpr(t1, rt); - tcg_gen_ext8s_tl(t0, t1); - gen_store_gpr(t0, rd); - break; - case OPC_SEH: - gen_load_gpr(t1, rt); - tcg_gen_ext16s_tl(t0, t1); - gen_store_gpr(t0, rd); - break; - default: /* Invalid */ - MIPS_INVAL("bshfl"); - generate_exception(ctx, EXCP_RI); - break; - } - tcg_temp_free(t0); - tcg_temp_free(t1); - } + gen_bshfl(ctx, op2, rt, rd); break; case OPC_RDHWR: check_insn(env, ctx, ISA_MIPS32R2); @@ -8056,28 +8083,7 @@ check_insn(env, ctx, ISA_MIPS64R2); check_mips_64(ctx); op2 = MASK_DBSHFL(ctx->opcode); - { - TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL); - TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL); - - switch (op2) { - case OPC_DSBH: - gen_load_gpr(t1, rt); - tcg_gen_helper_1_1(do_dsbh, t0, t1); - break; - case OPC_DSHD: - gen_load_gpr(t1, rt); - tcg_gen_helper_1_1(do_dshd, t0, t1); - break; - default: /* Invalid */ - MIPS_INVAL("dbshfl"); - generate_exception(ctx, EXCP_RI); - break; - } - gen_store_gpr(t0, rd); - tcg_temp_free(t0); - tcg_temp_free(t1); - } + gen_bshfl(ctx, op2, rt, rd); break; #endif default: /* Invalid */