From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L2rGN-0002k6-S1 for qemu-devel@nongnu.org; Wed, 19 Nov 2008 12:54:51 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L2rGN-0002jk-Br for qemu-devel@nongnu.org; Wed, 19 Nov 2008 12:54:51 -0500 Received: from [199.232.76.173] (port=43599 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L2rGN-0002jh-2j for qemu-devel@nongnu.org; Wed, 19 Nov 2008 12:54:51 -0500 Received: from savannah.gnu.org ([199.232.41.3]:36539 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1L2rGM-0004Og-Q9 for qemu-devel@nongnu.org; Wed, 19 Nov 2008 12:54:50 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1L2rGL-0003id-PW for qemu-devel@nongnu.org; Wed, 19 Nov 2008 17:54:49 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1L2rGL-0003iZ-EE for qemu-devel@nongnu.org; Wed, 19 Nov 2008 17:54:49 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Wed, 19 Nov 2008 17:54:49 +0000 Subject: [Qemu-devel] [5756] target-ppc: fix TCG type errors introduced in r5754 Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5756 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5756 Author: aurel32 Date: 2008-11-19 17:54:49 +0000 (Wed, 19 Nov 2008) Log Message: ----------- target-ppc: fix TCG type errors introduced in r5754 Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/target-ppc/translate.c Modified: trunk/target-ppc/translate.c =================================================================== --- trunk/target-ppc/translate.c 2008-11-19 17:41:58 UTC (rev 5755) +++ trunk/target-ppc/translate.c 2008-11-19 17:54:49 UTC (rev 5756) @@ -243,31 +243,31 @@ #endif } -static always_inline void gen_compute_fprf (TCGv arg, int set_fprf, int set_rc) +static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc) { - TCGv t0 = tcg_temp_new_i32(); + TCGv_i32 t0 = tcg_temp_new_i32(); if (set_fprf != 0) { /* This case might be optimized later */ #if defined(OPTIMIZE_FPRF_UPDATE) *gen_fprf_ptr++ = gen_opc_ptr; #endif - tcg_gen_movi_tl(t0, 1); + tcg_gen_movi_i32(t0, 1); gen_helper_compute_fprf(t0, arg, t0); if (unlikely(set_rc)) { - tcg_gen_movi_i32(cpu_crf[1], t0); + tcg_gen_mov_i32(cpu_crf[1], t0); } gen_helper_float_check_status(); } else if (unlikely(set_rc)) { /* We always need to compute fpcc */ - tcg_gen_movi_tl(t0, 0); + tcg_gen_movi_i32(t0, 0); gen_helper_compute_fprf(t0, arg, t0); - tcg_gen_movi_i32(cpu_crf[1], t0); + tcg_gen_mov_i32(cpu_crf[1], t0); if (set_fprf) gen_helper_float_check_status(); } - tcg_temp_free(t0); + tcg_temp_free_i32(t0); } static always_inline void gen_optimize_fprf (void) @@ -2385,9 +2385,9 @@ gen_reset_fpstatus(); /* XXX: we pretend we can only do IEEE floating-point computations */ if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { - TCGv t0 = tcg_const_tl(crb); + TCGv_i32 t0 = tcg_const_i32(crb); gen_helper_fpscr_setbit(t0); - tcg_temp_free(t0); + tcg_temp_free_i32(t0); } if (unlikely(Rc(ctx->opcode) != 0)) { tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); @@ -2399,7 +2399,7 @@ /* mtfsf */ GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) { - TCGv t0; + TCGv_i32 t0; if (unlikely(!ctx->fpu_enabled)) { GEN_EXCP_NO_FP(ctx); @@ -2409,7 +2409,7 @@ gen_reset_fpstatus(); t0 = tcg_const_i32(FM(ctx->opcode)); gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0); - tcg_temp_free(t0); + tcg_temp_free_i32(t0); if (unlikely(Rc(ctx->opcode) != 0)) { tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); } @@ -2421,7 +2421,8 @@ GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT) { int bf, sh; - TCGv t0, t1; + TCGv_i64 t0; + TCGv_i32 t1; if (unlikely(!ctx->fpu_enabled)) { GEN_EXCP_NO_FP(ctx); @@ -2431,11 +2432,11 @@ sh = 7 - bf; gen_optimize_fprf(); gen_reset_fpstatus(); - t0 = tcg_const_tl(FPIMM(ctx->opcode) << (4 * sh)); + t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh)); t1 = tcg_const_i32(1 << sh); gen_helper_store_fpscr(t0, t1); - tcg_temp_free(t0); - tcg_temp_free(t1); + tcg_temp_free_i64(t0); + tcg_temp_free_i32(t1); if (unlikely(Rc(ctx->opcode) != 0)) { tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); }