From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L3dDB-0002iN-Ve for qemu-devel@nongnu.org; Fri, 21 Nov 2008 16:06:46 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L3dDB-0002hL-5I for qemu-devel@nongnu.org; Fri, 21 Nov 2008 16:06:45 -0500 Received: from [199.232.76.173] (port=52842 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L3dDB-0002h9-0c for qemu-devel@nongnu.org; Fri, 21 Nov 2008 16:06:45 -0500 Received: from savannah.gnu.org ([199.232.41.3]:35039 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1L3dDA-0003Ru-L5 for qemu-devel@nongnu.org; Fri, 21 Nov 2008 16:06:44 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1L3dDA-0000Xr-1h for qemu-devel@nongnu.org; Fri, 21 Nov 2008 21:06:44 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1L3dD9-0000Xa-LL for qemu-devel@nongnu.org; Fri, 21 Nov 2008 21:06:43 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Fri, 21 Nov 2008 21:06:43 +0000 Subject: [Qemu-devel] [5768] SH4: Use qemu_irq in timer emulation. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5768 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5768 Author: aurel32 Date: 2008-11-21 21:06:42 +0000 (Fri, 21 Nov 2008) Log Message: ----------- SH4: Use qemu_irq in timer emulation. * hw/sh.h (tmu012_init): Accept qemu_irq, not intc_source. * hw/sh7750.c (sh7750_init): Pass qemu_irq to tmu012_init. * hw/sh_intc.c (sh_intc_set_irq): New. (sh_intc_init): Allocate irqs. * hw/sh_intc.h (struct intc_desc): New field irqs. * hw/sh_timer.c (sh_timer_state): Use qemu_irq, not intc_source. (sh_timer_update): Use qemu_set_irq, not sh_intc_toggle_source. (sh_timer_init, tmu012_init): Adjust. (Vladimir Prus) Modified Paths: -------------- trunk/hw/sh.h trunk/hw/sh7750.c trunk/hw/sh_intc.c trunk/hw/sh_intc.h trunk/hw/sh_timer.c Modified: trunk/hw/sh.h =================================================================== --- trunk/hw/sh.h 2008-11-21 17:26:23 UTC (rev 5767) +++ trunk/hw/sh.h 2008-11-21 21:06:42 UTC (rev 5768) @@ -28,8 +28,8 @@ #define TMU012_FEAT_3CHAN (1 << 1) #define TMU012_FEAT_EXTCLK (1 << 2) void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq, - struct intc_source *ch0_irq, struct intc_source *ch1_irq, - struct intc_source *ch2_irq0, struct intc_source *ch2_irq1); + qemu_irq ch0_irq, qemu_irq ch1_irq, + qemu_irq ch2_irq0, qemu_irq ch2_irq1); /* sh_serial.c */ Modified: trunk/hw/sh7750.c =================================================================== --- trunk/hw/sh7750.c 2008-11-21 17:26:23 UTC (rev 5767) +++ trunk/hw/sh7750.c 2008-11-21 21:06:42 UTC (rev 5768) @@ -678,10 +678,10 @@ tmu012_init(0x1fd80000, TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, s->periph_freq, - sh_intc_source(&s->intc, TMU0), - sh_intc_source(&s->intc, TMU1), - sh_intc_source(&s->intc, TMU2_TUNI), - sh_intc_source(&s->intc, TMU2_TICPI)); + s->intc.irqs[TMU0], + s->intc.irqs[TMU1], + s->intc.irqs[TMU2_TUNI], + s->intc.irqs[TMU2_TICPI]); if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) { sh_intc_register_sources(&s->intc, @@ -700,8 +700,8 @@ _INTC_ARRAY(vectors_tmu34), NULL, 0); tmu012_init(0x1e100000, 0, s->periph_freq, - sh_intc_source(&s->intc, TMU3), - sh_intc_source(&s->intc, TMU4), + s->intc.irqs[TMU3], + s->intc.irqs[TMU4], NULL, NULL); } Modified: trunk/hw/sh_intc.c =================================================================== --- trunk/hw/sh_intc.c 2008-11-21 17:26:23 UTC (rev 5767) +++ trunk/hw/sh_intc.c 2008-11-21 21:06:42 UTC (rev 5768) @@ -73,6 +73,14 @@ } } +void sh_intc_set_irq (void *opaque, int n, int level) +{ + struct intc_desc *desc = opaque; + struct intc_source *source = &(desc->sources[n]); + + sh_intc_toggle_source(source, 0, level ? 1 : -1); +} + int sh_intc_get_pending_vector(struct intc_desc *desc, int imask) { unsigned int i; @@ -428,6 +436,8 @@ source->parent = desc; } + + desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources); desc->iomemtype = cpu_register_io_memory(0, sh_intc_readfn, sh_intc_writefn, desc); Modified: trunk/hw/sh_intc.h =================================================================== --- trunk/hw/sh_intc.h 2008-11-21 17:26:23 UTC (rev 5767) +++ trunk/hw/sh_intc.h 2008-11-21 21:06:42 UTC (rev 5768) @@ -1,6 +1,9 @@ #ifndef __SH_INTC_H__ #define __SH_INTC_H__ +#include "qemu-common.h" +#include "irq.h" + typedef unsigned char intc_enum; struct intc_vect { @@ -43,13 +46,13 @@ }; struct intc_desc { + qemu_irq *irqs; struct intc_source *sources; int nr_sources; struct intc_mask_reg *mask_regs; int nr_mask_regs; struct intc_prio_reg *prio_regs; int nr_prio_regs; - int iomemtype; int pending; /* number of interrupt sources that has pending set */ }; Modified: trunk/hw/sh_timer.c =================================================================== --- trunk/hw/sh_timer.c 2008-11-21 17:26:23 UTC (rev 5767) +++ trunk/hw/sh_timer.c 2008-11-21 21:06:42 UTC (rev 5768) @@ -36,7 +36,7 @@ int old_level; int feat; int enabled; - struct intc_source *irq; + qemu_irq irq; } sh_timer_state; /* Check all active timers, and schedule the next timer interrupt. */ @@ -46,7 +46,7 @@ int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); if (new_level != s->old_level) - sh_intc_toggle_source(s->irq, 0, new_level ? 1 : -1); + qemu_set_irq (s->irq, new_level); s->old_level = s->int_level; s->int_level = new_level; @@ -185,7 +185,7 @@ sh_timer_update(s); } -static void *sh_timer_init(uint32_t freq, int feat, struct intc_source *irq) +static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) { sh_timer_state *s; QEMUBH *bh; @@ -307,8 +307,8 @@ }; void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq, - struct intc_source *ch0_irq, struct intc_source *ch1_irq, - struct intc_source *ch2_irq0, struct intc_source *ch2_irq1) + qemu_irq ch0_irq, qemu_irq ch1_irq, + qemu_irq ch2_irq0, qemu_irq ch2_irq1) { int iomemtype; tmu012_state *s;