From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L3pQf-0001Cf-LA for qemu-devel@nongnu.org; Sat, 22 Nov 2008 05:09:29 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L3pQf-0001C0-4y for qemu-devel@nongnu.org; Sat, 22 Nov 2008 05:09:29 -0500 Received: from [199.232.76.173] (port=40668 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L3pQe-0001Bu-I9 for qemu-devel@nongnu.org; Sat, 22 Nov 2008 05:09:28 -0500 Received: from savannah.gnu.org ([199.232.41.3]:33905 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1L3pQe-0001r1-7e for qemu-devel@nongnu.org; Sat, 22 Nov 2008 05:09:28 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1L3pQd-0004if-Rv for qemu-devel@nongnu.org; Sat, 22 Nov 2008 10:09:27 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1L3pQd-0004ib-KU for qemu-devel@nongnu.org; Sat, 22 Nov 2008 10:09:27 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Sat, 22 Nov 2008 10:09:27 +0000 Subject: [Qemu-devel] [5773] target-sh4: fix 64-bit fmov to/from memory Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5773 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5773 Author: aurel32 Date: 2008-11-22 10:09:27 +0000 (Sat, 22 Nov 2008) Log Message: ----------- target-sh4: fix 64-bit fmov to/from memory When loading/storing a register pair, the even-numbered register always maps to the low 32 bits of memory independently of target endian configuration. Signed-off-by: Mans Rullgard Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/target-sh4/translate.c Modified: trunk/target-sh4/translate.c =================================================================== --- trunk/target-sh4/translate.c 2008-11-22 10:09:17 UTC (rev 5772) +++ trunk/target-sh4/translate.c 2008-11-22 10:09:27 UTC (rev 5773) @@ -991,31 +991,37 @@ return; case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ if (ctx->fpscr & FPSCR_SZ) { - TCGv_i64 fp = tcg_temp_new_i64(); - gen_load_fpr64(fp, XREG(B7_4)); - tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx); - tcg_temp_free_i64(fp); + TCGv addr_hi = tcg_temp_new(); + int fr = XREG(B7_4); + tcg_gen_addi_i32(addr_hi, REG(B11_8), 4); + tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx); + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx); + tcg_temp_free(addr_hi); } else { tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx); } return; case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ if (ctx->fpscr & FPSCR_SZ) { - TCGv_i64 fp = tcg_temp_new_i64(); - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx); - gen_store_fpr64(fp, XREG(B11_8)); - tcg_temp_free_i64(fp); + TCGv addr_hi = tcg_temp_new(); + int fr = XREG(B11_8); + tcg_gen_addi_i32(addr_hi, REG(B7_4), 4); + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx); + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx); + tcg_temp_free(addr_hi); } else { tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx); } return; case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ if (ctx->fpscr & FPSCR_SZ) { - TCGv_i64 fp = tcg_temp_new_i64(); - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx); - gen_store_fpr64(fp, XREG(B11_8)); - tcg_temp_free_i64(fp); - tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8); + TCGv addr_hi = tcg_temp_new(); + int fr = XREG(B11_8); + tcg_gen_addi_i32(addr_hi, REG(B7_4), 4); + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx); + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx); + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8); + tcg_temp_free(addr_hi); } else { tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); @@ -1023,16 +1029,14 @@ return; case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ if (ctx->fpscr & FPSCR_SZ) { - TCGv addr; - TCGv_i64 fp; - addr = tcg_temp_new(); + TCGv addr = tcg_temp_new_i32(); + int fr = XREG(B7_4); + tcg_gen_subi_i32(addr, REG(B11_8), 4); + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx); tcg_gen_subi_i32(addr, REG(B11_8), 8); - fp = tcg_temp_new_i64(); - gen_load_fpr64(fp, XREG(B7_4)); - tcg_gen_qemu_st64(fp, addr, ctx->memidx); - tcg_temp_free_i64(fp); + tcg_gen_qemu_st32(cpu_fregs[fr ], addr, ctx->memidx); + tcg_gen_mov_i32(REG(B11_8), addr); tcg_temp_free(addr); - tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8); } else { TCGv addr; addr = tcg_temp_new_i32(); @@ -1047,10 +1051,10 @@ TCGv addr = tcg_temp_new_i32(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); if (ctx->fpscr & FPSCR_SZ) { - TCGv_i64 fp = tcg_temp_new_i64(); - tcg_gen_qemu_ld64(fp, addr, ctx->memidx); - gen_store_fpr64(fp, XREG(B11_8)); - tcg_temp_free_i64(fp); + int fr = XREG(B11_8); + tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx); + tcg_gen_addi_i32(addr, addr, 4); + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx); } else { tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx); } @@ -1062,10 +1066,10 @@ TCGv addr = tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); if (ctx->fpscr & FPSCR_SZ) { - TCGv_i64 fp = tcg_temp_new_i64(); - gen_load_fpr64(fp, XREG(B7_4)); - tcg_gen_qemu_st64(fp, addr, ctx->memidx); - tcg_temp_free_i64(fp); + int fr = XREG(B7_4); + tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx); + tcg_gen_addi_i32(addr, addr, 4); + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx); } else { tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx); }