From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L4Hr9-0004DF-6T for qemu-devel@nongnu.org; Sun, 23 Nov 2008 11:30:43 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L4Hr8-0004Cr-G7 for qemu-devel@nongnu.org; Sun, 23 Nov 2008 11:30:42 -0500 Received: from [199.232.76.173] (port=52915 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L4Hr7-0004Ci-TX for qemu-devel@nongnu.org; Sun, 23 Nov 2008 11:30:41 -0500 Received: from savannah.gnu.org ([199.232.41.3]:40955 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1L4Hr7-0005AK-Ec for qemu-devel@nongnu.org; Sun, 23 Nov 2008 11:30:41 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1L4Hr6-0002cW-SA for qemu-devel@nongnu.org; Sun, 23 Nov 2008 16:30:40 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1L4Hr6-0002cS-H1 for qemu-devel@nongnu.org; Sun, 23 Nov 2008 16:30:40 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Sun, 23 Nov 2008 16:30:40 +0000 Subject: [Qemu-devel] [5785] target-ppc: fix access_type usage Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5785 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5785 Author: aurel32 Date: 2008-11-23 16:30:40 +0000 (Sun, 23 Nov 2008) Log Message: ----------- target-ppc: fix access_type usage Write env->access_type before a load/store operation instead of relying on the name of the dyngen operation. Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/target-ppc/translate.c Modified: trunk/target-ppc/translate.c =================================================================== --- trunk/target-ppc/translate.c 2008-11-23 16:30:28 UTC (rev 5784) +++ trunk/target-ppc/translate.c 2008-11-23 16:30:40 UTC (rev 5785) @@ -67,6 +67,7 @@ static TCGv cpu_lr; static TCGv cpu_xer; static TCGv_i32 cpu_fpscr; +static TCGv_i32 cpu_access_type; /* dyngen register indexes */ static TCGv cpu_T[3]; @@ -186,6 +187,9 @@ cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, fpscr), "fpscr"); + cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, access_type), "access_type"); + /* register helpers */ #define GEN_HELPER 2 #include "helper.h" @@ -281,6 +285,11 @@ #endif } +static always_inline void gen_set_access_type(int access_type) +{ + tcg_gen_movi_i32(cpu_access_type, access_type); +} + static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip) { #if defined(TARGET_PPC64) @@ -2780,6 +2789,7 @@ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \ { \ TCGv EA = tcg_temp_new(); \ + gen_set_access_type(ACCESS_INT); \ gen_addr_imm_index(EA, ctx, 0); \ gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ tcg_temp_free(EA); \ @@ -2795,6 +2805,7 @@ return; \ } \ EA = tcg_temp_new(); \ + gen_set_access_type(ACCESS_INT); \ if (type == PPC_64B) \ gen_addr_imm_index(EA, ctx, 0x03); \ else \ @@ -2814,6 +2825,7 @@ return; \ } \ EA = tcg_temp_new(); \ + gen_set_access_type(ACCESS_INT); \ gen_addr_reg_index(EA, ctx); \ gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ @@ -2824,6 +2836,7 @@ GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \ { \ TCGv EA = tcg_temp_new(); \ + gen_set_access_type(ACCESS_INT); \ gen_addr_reg_index(EA, ctx); \ gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \ tcg_temp_free(EA); \ @@ -2863,6 +2876,7 @@ } } EA = tcg_temp_new(); + gen_set_access_type(ACCESS_INT); gen_addr_imm_index(EA, ctx, 0x03); if (ctx->opcode & 0x02) { /* lwa (lwau is undefined) */ @@ -2901,6 +2915,7 @@ return; } EA = tcg_temp_new(); + gen_set_access_type(ACCESS_INT); gen_addr_imm_index(EA, ctx, 0x0F); gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx); tcg_gen_addi_tl(EA, EA, 8); @@ -2915,6 +2930,7 @@ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \ { \ TCGv EA = tcg_temp_new(); \ + gen_set_access_type(ACCESS_INT); \ gen_addr_imm_index(EA, ctx, 0); \ gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ tcg_temp_free(EA); \ @@ -2929,6 +2945,7 @@ return; \ } \ EA = tcg_temp_new(); \ + gen_set_access_type(ACCESS_INT); \ if (type == PPC_64B) \ gen_addr_imm_index(EA, ctx, 0x03); \ else \ @@ -2947,6 +2964,7 @@ return; \ } \ EA = tcg_temp_new(); \ + gen_set_access_type(ACCESS_INT); \ gen_addr_reg_index(EA, ctx); \ gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ @@ -2957,6 +2975,7 @@ GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \ { \ TCGv EA = tcg_temp_new(); \ + gen_set_access_type(ACCESS_INT); \ gen_addr_reg_index(EA, ctx); \ gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \ tcg_temp_free(EA); \ @@ -3002,6 +3021,7 @@ return; } EA = tcg_temp_new(); + gen_set_access_type(ACCESS_INT); gen_addr_imm_index(EA, ctx, 0x03); gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx); tcg_gen_addi_tl(EA, EA, 8); @@ -3017,6 +3037,7 @@ } } EA = tcg_temp_new(); + gen_set_access_type(ACCESS_INT); gen_addr_imm_index(EA, ctx, 0x03); gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx); if (Rc(ctx->opcode)) @@ -3240,6 +3261,7 @@ { /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); + gen_set_access_type(ACCESS_RES); gen_addr_reg_index(cpu_T[0], ctx); op_lwarx(); tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); @@ -3250,6 +3272,7 @@ { /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); + gen_set_access_type(ACCESS_RES); gen_addr_reg_index(cpu_T[0], ctx); tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); op_stwcx(); @@ -3270,6 +3293,7 @@ { /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); + gen_set_access_type(ACCESS_RES); gen_addr_reg_index(cpu_T[0], ctx); op_ldarx(); tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); @@ -3280,6 +3304,7 @@ { /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); + gen_set_access_type(ACCESS_RES); gen_addr_reg_index(cpu_T[0], ctx); tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); op_stdcx(); @@ -3307,6 +3332,7 @@ GEN_EXCP_NO_FP(ctx); \ return; \ } \ + gen_set_access_type(ACCESS_FLOAT); \ gen_addr_imm_index(cpu_T[0], ctx, 0); \ op_ldst(l##width); \ tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ @@ -3323,6 +3349,7 @@ GEN_EXCP_INVAL(ctx); \ return; \ } \ + gen_set_access_type(ACCESS_FLOAT); \ gen_addr_imm_index(cpu_T[0], ctx, 0); \ op_ldst(l##width); \ tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ @@ -3340,6 +3367,7 @@ GEN_EXCP_INVAL(ctx); \ return; \ } \ + gen_set_access_type(ACCESS_FLOAT); \ gen_addr_reg_index(cpu_T[0], ctx); \ op_ldst(l##width); \ tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ @@ -3353,6 +3381,7 @@ GEN_EXCP_NO_FP(ctx); \ return; \ } \ + gen_set_access_type(ACCESS_FLOAT); \ gen_addr_reg_index(cpu_T[0], ctx); \ op_ldst(l##width); \ tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ @@ -3378,6 +3407,7 @@ GEN_EXCP_NO_FP(ctx); \ return; \ } \ + gen_set_access_type(ACCESS_FLOAT); \ gen_addr_imm_index(cpu_T[0], ctx, 0); \ tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \ op_ldst(st##width); \ @@ -3394,6 +3424,7 @@ GEN_EXCP_INVAL(ctx); \ return; \ } \ + gen_set_access_type(ACCESS_FLOAT); \ gen_addr_imm_index(cpu_T[0], ctx, 0); \ tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \ op_ldst(st##width); \ @@ -3411,6 +3442,7 @@ GEN_EXCP_INVAL(ctx); \ return; \ } \ + gen_set_access_type(ACCESS_FLOAT); \ gen_addr_reg_index(cpu_T[0], ctx); \ tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \ op_ldst(st##width); \ @@ -3424,6 +3456,7 @@ GEN_EXCP_NO_FP(ctx); \ return; \ } \ + gen_set_access_type(ACCESS_FLOAT); \ gen_addr_reg_index(cpu_T[0], ctx); \ tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \ op_ldst(st##width); \ @@ -4011,6 +4044,7 @@ { /* XXX: specification says this is treated as a load by the MMU */ TCGv t0 = tcg_temp_new(); + gen_set_access_type(ACCESS_CACHE); gen_addr_reg_index(t0, ctx); gen_qemu_ld8u(t0, t0, ctx->mem_idx); tcg_temp_free(t0); @@ -4028,6 +4062,7 @@ return; } EA = tcg_temp_new(); + gen_set_access_type(ACCESS_CACHE); gen_addr_reg_index(EA, ctx); val = tcg_temp_new(); /* XXX: specification says this should be treated as a store by the MMU */ @@ -4043,6 +4078,7 @@ { /* XXX: specification say this is treated as a load by the MMU */ TCGv t0 = tcg_temp_new(); + gen_set_access_type(ACCESS_CACHE); gen_addr_reg_index(t0, ctx); gen_qemu_ld8u(t0, t0, ctx->mem_idx); tcg_temp_free(t0); @@ -4428,6 +4464,7 @@ GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN) { /* Should check EAR[E] & alignment ! */ + gen_set_access_type(ACCESS_RES); gen_addr_reg_index(cpu_T[0], ctx); op_eciwx(); tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); @@ -5512,6 +5549,7 @@ return; } EA = tcg_temp_new(); + gen_set_access_type(ACCESS_CACHE); gen_addr_reg_index(EA, ctx); val = tcg_temp_new(); gen_qemu_ld32u(val, EA, ctx->mem_idx); @@ -7630,41 +7668,5 @@ void gen_pc_load(CPUState *env, TranslationBlock *tb, unsigned long searched_pc, int pc_pos, void *puc) { - int type, c; - /* for PPC, we need to look at the micro operation to get the - * access type */ env->nip = gen_opc_pc[pc_pos]; - c = gen_opc_buf[pc_pos]; - switch(c) { -#if defined(CONFIG_USER_ONLY) -#define CASE3(op)\ - case INDEX_op_ ## op ## _raw -#else -#define CASE3(op)\ - case INDEX_op_ ## op ## _user:\ - case INDEX_op_ ## op ## _kernel:\ - case INDEX_op_ ## op ## _hypv -#endif - - CASE3(stfd): - CASE3(stfs): - CASE3(lfd): - CASE3(lfs): - type = ACCESS_FLOAT; - break; - CASE3(lwarx): - type = ACCESS_RES; - break; - CASE3(stwcx): - type = ACCESS_RES; - break; - CASE3(eciwx): - CASE3(ecowx): - type = ACCESS_EXT; - break; - default: - type = ACCESS_INT; - break; - } - env->access_type = type; }