From: Andrzej Zaborowski <balrogg@gmail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [5847] arm: Don't potentially overwrite input registers in add2, sub2.
Date: Mon, 01 Dec 2008 11:57:22 +0000 [thread overview]
Message-ID: <E1L77P0-0002nR-1F@cvs.savannah.gnu.org> (raw)
Revision: 5847
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5847
Author: balrog
Date: 2008-12-01 11:57:21 +0000 (Mon, 01 Dec 2008)
Log Message:
-----------
arm: Don't potentially overwrite input registers in add2, sub2.
According to malc TCG will often genereate an add2/sub2/mul2 with low
half of the output in the same register as high half of one of the
inputs, so account for that.
Modified Paths:
--------------
trunk/tcg/arm/tcg-target.c
Modified: trunk/tcg/arm/tcg-target.c
===================================================================
--- trunk/tcg/arm/tcg-target.c 2008-12-01 02:19:41 UTC (rev 5846)
+++ trunk/tcg/arm/tcg-target.c 2008-12-01 11:57:21 UTC (rev 5847)
@@ -295,10 +295,19 @@
int cond, int opc0, int opc1, int rd0, int rd1,
int rn0, int rn1, int rm0, int rm1, int shift)
{
- tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
- (rn0 << 16) | (rd0 << 12) | shift | rm0);
- tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
- (rn1 << 16) | (rd1 << 12) | shift | rm1);
+ if (rd0 == rn1 || rd0 == rm1) {
+ tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
+ (rn0 << 16) | (8 << 12) | shift | rm0);
+ tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
+ (rn1 << 16) | (rd1 << 12) | shift | rm1);
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ rd0, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
+ } else {
+ tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
+ (rn0 << 16) | (rd0 << 12) | shift | rm0);
+ tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
+ (rn1 << 16) | (rd1 << 12) | shift | rm1);
+ }
}
static inline void tcg_out_dat_imm(TCGContext *s,
reply other threads:[~2008-12-01 11:57 UTC|newest]
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