From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L7ZP8-0007YQ-HA for qemu-devel@nongnu.org; Tue, 02 Dec 2008 12:51:22 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L7ZP8-0007Xz-7r for qemu-devel@nongnu.org; Tue, 02 Dec 2008 12:51:22 -0500 Received: from [199.232.76.173] (port=57166 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L7ZP7-0007Xu-M0 for qemu-devel@nongnu.org; Tue, 02 Dec 2008 12:51:21 -0500 Received: from savannah.gnu.org ([199.232.41.3]:45516 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1L7ZP6-0007qC-Sc for qemu-devel@nongnu.org; Tue, 02 Dec 2008 12:51:21 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1L7ZP6-00055U-CW for qemu-devel@nongnu.org; Tue, 02 Dec 2008 17:51:20 +0000 Received: from blueswir1 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1L7ZP6-00055F-2Q for qemu-devel@nongnu.org; Tue, 02 Dec 2008 17:51:20 +0000 MIME-Version: 1.0 Errors-To: blueswir1 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Blue Swirl Message-Id: Date: Tue, 02 Dec 2008 17:51:20 +0000 Subject: [Qemu-devel] [5854] Remove address masking after some rearranging Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5854 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5854 Author: blueswir1 Date: 2008-12-02 17:51:19 +0000 (Tue, 02 Dec 2008) Log Message: ----------- Remove address masking after some rearranging Modified Paths: -------------- trunk/hw/slavio_intctl.c trunk/hw/slavio_misc.c Modified: trunk/hw/slavio_intctl.c =================================================================== --- trunk/hw/slavio_intctl.c 2008-12-02 17:47:02 UTC (rev 5853) +++ trunk/hw/slavio_intctl.c 2008-12-02 17:51:19 UTC (rev 5854) @@ -49,8 +49,9 @@ #define MAX_CPUS 16 #define MAX_PILS 16 +struct SLAVIO_CPUINTCTLState; + typedef struct SLAVIO_INTCTLState { - uint32_t intreg_pending[MAX_CPUS]; uint32_t intregm_pending; uint32_t intregm_disabled; uint32_t target_cpu; @@ -61,13 +62,18 @@ const uint32_t *intbit_to_level; uint32_t cputimer_lbit, cputimer_mbit; uint32_t pil_out[MAX_CPUS]; + struct SLAVIO_CPUINTCTLState *slaves[MAX_CPUS]; } SLAVIO_INTCTLState; +typedef struct SLAVIO_CPUINTCTLState { + uint32_t intreg_pending; + SLAVIO_INTCTLState *master; + uint32_t cpu; +} SLAVIO_CPUINTCTLState; + #define INTCTL_MAXADDR 0xf #define INTCTL_SIZE (INTCTL_MAXADDR + 1) -#define INTCTLM_MAXADDR 0x13 -#define INTCTLM_SIZE (INTCTLM_MAXADDR + 1) -#define INTCTLM_MASK 0x1f +#define INTCTLM_SIZE 0x14 #define MASTER_IRQ_MASK ~0x0fa2007f #define MASTER_DISABLE 0x80000000 #define CPU_SOFTIRQ_MASK 0xfffe0000 @@ -75,20 +81,18 @@ #define CPU_IRQ_INT15_IN 0x0004000 #define CPU_IRQ_INT15_MASK 0x80000000 -static void slavio_check_interrupts(void *opaque); +static void slavio_check_interrupts(SLAVIO_INTCTLState *s); // per-cpu interrupt controller static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr) { - SLAVIO_INTCTLState *s = opaque; + SLAVIO_CPUINTCTLState *s = opaque; uint32_t saddr, ret; - int cpu; - cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12; - saddr = (addr & INTCTL_MAXADDR) >> 2; + saddr = addr >> 2; switch (saddr) { case 0: - ret = s->intreg_pending[cpu]; + ret = s->intreg_pending; break; default: ret = 0; @@ -102,29 +106,27 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) { - SLAVIO_INTCTLState *s = opaque; + SLAVIO_CPUINTCTLState *s = opaque; uint32_t saddr; - int cpu; - cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12; - saddr = (addr & INTCTL_MAXADDR) >> 2; + saddr = addr >> 2; DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val); switch (saddr) { case 1: // clear pending softints if (val & CPU_IRQ_INT15_IN) val |= CPU_IRQ_INT15_MASK; val &= CPU_SOFTIRQ_MASK; - s->intreg_pending[cpu] &= ~val; - slavio_check_interrupts(s); - DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, - s->intreg_pending[cpu]); + s->intreg_pending &= ~val; + slavio_check_interrupts(s->master); + DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val, + s->intreg_pending); break; case 2: // set softint val &= CPU_SOFTIRQ_MASK; - s->intreg_pending[cpu] |= val; - slavio_check_interrupts(s); - DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, - s->intreg_pending[cpu]); + s->intreg_pending |= val; + slavio_check_interrupts(s->master); + DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val, + s->intreg_pending); break; default: break; @@ -149,7 +151,7 @@ SLAVIO_INTCTLState *s = opaque; uint32_t saddr, ret; - saddr = (addr & INTCTLM_MASK) >> 2; + saddr = addr >> 2; switch (saddr) { case 0: ret = s->intregm_pending & ~MASTER_DISABLE; @@ -175,7 +177,7 @@ SLAVIO_INTCTLState *s = opaque; uint32_t saddr; - saddr = (addr & INTCTLM_MASK) >> 2; + saddr = addr >> 2; DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val); switch (saddr) { case 2: // clear (enable) @@ -223,7 +225,8 @@ int i; for (i = 0; i < MAX_CPUS; i++) { - term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]); + term_printf("per-cpu %d: pending 0x%08x\n", i, + s->slaves[i]->intreg_pending); } term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled); @@ -247,9 +250,8 @@ #endif } -static void slavio_check_interrupts(void *opaque) +static void slavio_check_interrupts(SLAVIO_INTCTLState *s) { - SLAVIO_INTCTLState *s = opaque; uint32_t pending = s->intregm_pending, pil_pending; unsigned int i, j; @@ -265,7 +267,7 @@ pil_pending |= 1 << s->intbit_to_level[j]; } } - pil_pending |= (s->intreg_pending[i] & CPU_SOFTIRQ_MASK) >> 16; + pil_pending |= (s->slaves[i]->intreg_pending & CPU_SOFTIRQ_MASK) >> 16; for (j = 0; j < MAX_PILS; j++) { if (pil_pending & (1 << j)) { @@ -298,10 +300,10 @@ s->irq_count[pil]++; #endif s->intregm_pending |= mask; - s->intreg_pending[s->target_cpu] |= 1 << pil; + s->slaves[s->target_cpu]->intreg_pending |= 1 << pil; } else { s->intregm_pending &= ~mask; - s->intreg_pending[s->target_cpu] &= ~(1 << pil); + s->slaves[s->target_cpu]->intreg_pending &= ~(1 << pil); } slavio_check_interrupts(s); } @@ -315,10 +317,10 @@ if (level) { s->intregm_pending |= s->cputimer_mbit; - s->intreg_pending[cpu] |= s->cputimer_lbit; + s->slaves[cpu]->intreg_pending |= s->cputimer_lbit; } else { s->intregm_pending &= ~s->cputimer_mbit; - s->intreg_pending[cpu] &= ~s->cputimer_lbit; + s->slaves[cpu]->intreg_pending &= ~s->cputimer_lbit; } slavio_check_interrupts(s); @@ -330,7 +332,7 @@ int i; for (i = 0; i < MAX_CPUS; i++) { - qemu_put_be32s(f, &s->intreg_pending[i]); + qemu_put_be32s(f, &s->slaves[i]->intreg_pending); } qemu_put_be32s(f, &s->intregm_pending); qemu_put_be32s(f, &s->intregm_disabled); @@ -346,7 +348,7 @@ return -EINVAL; for (i = 0; i < MAX_CPUS; i++) { - qemu_get_be32s(f, &s->intreg_pending[i]); + qemu_get_be32s(f, &s->slaves[i]->intreg_pending); } qemu_get_be32s(f, &s->intregm_pending); qemu_get_be32s(f, &s->intregm_disabled); @@ -361,7 +363,7 @@ int i; for (i = 0; i < MAX_CPUS; i++) { - s->intreg_pending[i] = 0; + s->slaves[i]->intreg_pending = 0; } s->intregm_disabled = ~MASTER_IRQ_MASK; s->intregm_pending = 0; @@ -376,6 +378,7 @@ { int slavio_intctl_io_memory, slavio_intctlm_io_memory, i; SLAVIO_INTCTLState *s; + SLAVIO_CPUINTCTLState *slave; s = qemu_mallocz(sizeof(SLAVIO_INTCTLState)); if (!s) @@ -383,12 +386,21 @@ s->intbit_to_level = intbit_to_level; for (i = 0; i < MAX_CPUS; i++) { + slave = qemu_mallocz(sizeof(SLAVIO_CPUINTCTLState)); + if (!slave) + return NULL; + + slave->cpu = i; + slave->master = s; + slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, - s); - cpu_register_physical_memory_offset(addr + i * TARGET_PAGE_SIZE, - INTCTL_SIZE, slavio_intctl_io_memory, i * TARGET_PAGE_SIZE); + slave); + cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE, + slavio_intctl_io_memory); + + s->slaves[i] = slave; s->cpu_irqs[i] = parent_irq[i]; } Modified: trunk/hw/slavio_misc.c =================================================================== --- trunk/hw/slavio_misc.c 2008-12-02 17:47:02 UTC (rev 5853) +++ trunk/hw/slavio_misc.c 2008-12-02 17:51:19 UTC (rev 5854) @@ -55,8 +55,7 @@ } MiscState; #define MISC_SIZE 1 -#define SYSCTRL_MAXADDR 3 -#define SYSCTRL_SIZE (SYSCTRL_MAXADDR + 1) +#define SYSCTRL_SIZE 4 #define LED_MAXADDR 1 #define LED_SIZE (LED_MAXADDR + 1) @@ -112,66 +111,100 @@ slavio_misc_update_irq(s); } -static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr, +static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr, + uint32_t val) +{ + MiscState *s = opaque; + + MISC_DPRINTF("Write config %2.2x\n", val & 0xff); + s->config = val & 0xff; + slavio_misc_update_irq(s); +} + +static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr) +{ + MiscState *s = opaque; + uint32_t ret = 0; + + ret = s->config; + MISC_DPRINTF("Read config %2.2x\n", ret); + return ret; +} + +static CPUReadMemoryFunc *slavio_cfg_mem_read[3] = { + slavio_cfg_mem_readb, + NULL, + NULL, +}; + +static CPUWriteMemoryFunc *slavio_cfg_mem_write[3] = { + slavio_cfg_mem_writeb, + NULL, + NULL, +}; + +static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) { MiscState *s = opaque; - switch (addr & MISC_MASK) { - case MISC_CFG: - MISC_DPRINTF("Write config %2.2x\n", val & 0xff); - s->config = val & 0xff; - slavio_misc_update_irq(s); - break; - case MISC_DIAG: - MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); - s->diag = val & 0xff; - break; - case MISC_MDM: - MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); - s->mctrl = val & 0xff; - break; - default: - break; - } + MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); + s->diag = val & 0xff; } -static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr) +static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr) { MiscState *s = opaque; uint32_t ret = 0; - switch (addr & MISC_MASK) { - case MISC_CFG: - ret = s->config; - MISC_DPRINTF("Read config %2.2x\n", ret); - break; - case MISC_DIAG: - ret = s->diag; - MISC_DPRINTF("Read diag %2.2x\n", ret); - break; - case MISC_MDM: - ret = s->mctrl; - MISC_DPRINTF("Read modem control %2.2x\n", ret); - break; - default: - break; - } + ret = s->diag; + MISC_DPRINTF("Read diag %2.2x\n", ret); return ret; } -static CPUReadMemoryFunc *slavio_misc_mem_read[3] = { - slavio_misc_mem_readb, +static CPUReadMemoryFunc *slavio_diag_mem_read[3] = { + slavio_diag_mem_readb, NULL, NULL, }; -static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = { - slavio_misc_mem_writeb, +static CPUWriteMemoryFunc *slavio_diag_mem_write[3] = { + slavio_diag_mem_writeb, NULL, NULL, }; +static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr, + uint32_t val) +{ + MiscState *s = opaque; + + MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); + s->mctrl = val & 0xff; +} + +static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr) +{ + MiscState *s = opaque; + uint32_t ret = 0; + + ret = s->mctrl; + MISC_DPRINTF("Read modem control %2.2x\n", ret); + return ret; +} + +static CPUReadMemoryFunc *slavio_mdm_mem_read[3] = { + slavio_mdm_mem_readb, + NULL, + NULL, +}; + +static CPUWriteMemoryFunc *slavio_mdm_mem_write[3] = { + slavio_mdm_mem_writeb, + NULL, + NULL, +}; + static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) { @@ -282,10 +315,9 @@ static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr) { MiscState *s = opaque; - uint32_t ret = 0, saddr; + uint32_t ret = 0; - saddr = addr & SYSCTRL_MAXADDR; - switch (saddr) { + switch (addr) { case 0: ret = s->sysctrl; break; @@ -301,12 +333,10 @@ uint32_t val) { MiscState *s = opaque; - uint32_t saddr; - saddr = addr & SYSCTRL_MAXADDR; MISC_DPRINTF("Write system control reg 0x" TARGET_FMT_plx " = %x\n", addr, val); - switch (saddr) { + switch (addr) { case 0: if (val & SYS_RESET) { s->sysctrl = SYS_RESETSTAT; @@ -333,10 +363,9 @@ static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr) { MiscState *s = opaque; - uint32_t ret = 0, saddr; + uint32_t ret = 0; - saddr = addr & LED_MAXADDR; - switch (saddr) { + switch (addr) { case 0: ret = s->leds; break; @@ -352,12 +381,10 @@ uint32_t val) { MiscState *s = opaque; - uint32_t saddr; - saddr = addr & LED_MAXADDR; MISC_DPRINTF("Write diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr, val); - switch (saddr) { + switch (addr) { case 0: s->leds = val; break; @@ -428,17 +455,21 @@ if (base) { /* 8 bit registers */ - io = cpu_register_io_memory(0, slavio_misc_mem_read, - slavio_misc_mem_write, s); + // Slavio control - cpu_register_physical_memory_offset(base + MISC_CFG, MISC_SIZE, io, - MISC_CFG); + io = cpu_register_io_memory(0, slavio_cfg_mem_read, + slavio_cfg_mem_write, s); + cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE, io); + // Diagnostics - cpu_register_physical_memory_offset(base + MISC_DIAG, MISC_SIZE, io, - MISC_DIAG); + io = cpu_register_io_memory(0, slavio_diag_mem_read, + slavio_diag_mem_write, s); + cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE, io); + // Modem control - cpu_register_physical_memory_offset(base + MISC_MDM, MISC_SIZE, io, - MISC_MDM); + io = cpu_register_io_memory(0, slavio_mdm_mem_read, + slavio_mdm_mem_write, s); + cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE, io); /* 16 bit registers */ io = cpu_register_io_memory(0, slavio_led_mem_read,