From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L9PNW-0008KT-AV for qemu-devel@nongnu.org; Sun, 07 Dec 2008 14:33:18 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L9PNV-0008JZ-Pi for qemu-devel@nongnu.org; Sun, 07 Dec 2008 14:33:17 -0500 Received: from [199.232.76.173] (port=39691 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L9PNV-0008JI-5H for qemu-devel@nongnu.org; Sun, 07 Dec 2008 14:33:17 -0500 Received: from savannah.gnu.org ([199.232.41.3]:43618 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1L9PNU-0003AK-OC for qemu-devel@nongnu.org; Sun, 07 Dec 2008 14:33:16 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1L9PNU-0002Fe-2K for qemu-devel@nongnu.org; Sun, 07 Dec 2008 19:33:16 +0000 Received: from balrog by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1L9PNT-0002Fa-SN for qemu-devel@nongnu.org; Sun, 07 Dec 2008 19:33:15 +0000 MIME-Version: 1.0 Errors-To: balrog Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Andrzej Zaborowski Message-Id: Date: Sun, 07 Dec 2008 19:33:15 +0000 Subject: [Qemu-devel] [5934] SH: improve the way sh7750 registers io memory (Takashi YOSHII). Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5934 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5934 Author: balrog Date: 2008-12-07 19:33:15 +0000 (Sun, 07 Dec 2008) Log Message: ----------- SH: improve the way sh7750 registers io memory (Takashi YOSHII). Fixes to be needed for commit #5849 "Change MMIO callbacks..." hw/sh7750.c: - Divide region of CPU control registers to avoid overlapping to peripheral modules. - Delete unused var "icr", which had moved to hw/sh_intc.c. hw/sm501.c: - Merge non page aligned palette registers into the region of control registers. Signed-off-by: Takashi YOSHII Signed-off-by: Andrzej Zaborowski Modified Paths: -------------- trunk/hw/sh7750.c trunk/hw/sm501.c Modified: trunk/hw/sh7750.c =================================================================== --- trunk/hw/sh7750.c 2008-12-07 19:30:18 UTC (rev 5933) +++ trunk/hw/sh7750.c 2008-12-07 19:33:15 UTC (rev 5934) @@ -60,7 +60,6 @@ uint16_t periph_portdirb; /* Direction seen from the peripherals */ sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */ - uint16_t icr; /* Cache */ uint32_t ccr; @@ -222,8 +221,6 @@ return porta_lines(s); case SH7750_PDTRB_A7: return portb_lines(s); - case 0x1fd00000: - return s->icr; default: error_access("word read", addr); assert(0); @@ -328,9 +325,6 @@ assert(0); } return; - case 0x1fd00000: - s->icr = mem_value; - return; default: error_access("word write", addr); assert(0); @@ -687,8 +681,12 @@ sh7750_io_memory = cpu_register_io_memory(0, sh7750_mem_read, sh7750_mem_write, s); - cpu_register_physical_memory_offset(0x1c000000, 0x04000000, - sh7750_io_memory, 0x1c000000); + cpu_register_physical_memory_offset(0x1f000000, 0x1000, + sh7750_io_memory, 0x1f000000); + cpu_register_physical_memory_offset(0x1f800000, 0x1000, + sh7750_io_memory, 0x1f800000); + cpu_register_physical_memory_offset(0x1fc00000, 0x1000, + sh7750_io_memory, 0x1fc00000); sh7750_mm_cache_and_tlb = cpu_register_io_memory(0, sh7750_mmct_read, Modified: trunk/hw/sm501.c =================================================================== --- trunk/hw/sm501.c 2008-12-07 19:30:18 UTC (rev 5933) +++ trunk/hw/sm501.c 2008-12-07 19:33:15 UTC (rev 5934) @@ -638,6 +638,32 @@ &sm501_system_config_write, }; +static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr) +{ + SM501State * s = (SM501State *)opaque; + SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr); + + /* TODO : consider BYTE/WORD access */ + /* TODO : consider endian */ + + assert(0 <= addr && addr < 0x400 * 3); + return *(uint32_t*)&s->dc_palette[addr]; +} + +static void sm501_palette_write(void *opaque, + target_phys_addr_t addr, uint32_t value) +{ + SM501State * s = (SM501State *)opaque; + SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n", + (int)addr, value); + + /* TODO : consider BYTE/WORD access */ + /* TODO : consider endian */ + + assert(0 <= addr && addr < 0x400 * 3); + *(uint32_t*)&s->dc_palette[addr] = value; +} + static uint32_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr) { SM501State * s = (SM501State *)opaque; @@ -719,6 +745,10 @@ ret = s->dc_crt_hwc_addr; break; + case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4: + ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE); + break; + default: printf("sm501 disp ctrl : not implemented register read." " addr=%x\n", (int)addr); @@ -823,6 +853,10 @@ s->dc_crt_hwc_addr = value & 0x0000FFFF; break; + case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4: + sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value); + break; + default: printf("sm501 disp ctrl : not implemented register write." " addr=%x, val=%x\n", (int)addr, value); @@ -842,45 +876,6 @@ &sm501_disp_ctrl_write, }; -static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr) -{ - SM501State * s = (SM501State *)opaque; - SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr); - - /* TODO : consider BYTE/WORD access */ - /* TODO : consider endian */ - - assert(0 <= addr && addr < 0x400 * 3); - return *(uint32_t*)&s->dc_palette[addr]; -} - -static void sm501_palette_write(void *opaque, - target_phys_addr_t addr, uint32_t value) -{ - SM501State * s = (SM501State *)opaque; - SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n", - (int)addr, value); - - /* TODO : consider BYTE/WORD access */ - /* TODO : consider endian */ - - assert(0 <= addr && addr < 0x400 * 3); - *(uint32_t*)&s->dc_palette[addr] = value; -} - -static CPUReadMemoryFunc *sm501_palette_readfn[] = { - &sm501_palette_read, - &sm501_palette_read, - &sm501_palette_read, -}; - -static CPUWriteMemoryFunc *sm501_palette_writefn[] = { - &sm501_palette_write, - &sm501_palette_write, - &sm501_palette_write, -}; - - /* draw line functions for all console modes */ #include "pixel_ops.h" @@ -1070,7 +1065,6 @@ SM501State * s; int sm501_system_config_index; int sm501_disp_ctrl_index; - int sm501_palette_index; /* allocate management data region */ s = (SM501State *)qemu_mallocz(sizeof(SM501State)); @@ -1098,14 +1092,8 @@ sm501_disp_ctrl_index = cpu_register_io_memory(0, sm501_disp_ctrl_readfn, sm501_disp_ctrl_writefn, s); cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_DC, - 0x400, sm501_disp_ctrl_index); + 0x1000, sm501_disp_ctrl_index); - sm501_palette_index = cpu_register_io_memory(0, sm501_palette_readfn, - sm501_palette_writefn, s); - cpu_register_physical_memory(base + MMIO_BASE_OFFSET - + SM501_DC + SM501_DC_PANEL_PALETTE, - 0x400 * 3, sm501_palette_index); - /* bridge to serial emulation module */ if (chr) serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,