From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L9PU1-0002Zs-OX for qemu-devel@nongnu.org; Sun, 07 Dec 2008 14:40:01 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L9PU0-0002Vv-2I for qemu-devel@nongnu.org; Sun, 07 Dec 2008 14:40:00 -0500 Received: from [199.232.76.173] (port=60284 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L9PTz-0002Vj-Uy for qemu-devel@nongnu.org; Sun, 07 Dec 2008 14:40:00 -0500 Received: from savannah.gnu.org ([199.232.41.3]:60493 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1L9PTz-0004JD-Ho for qemu-devel@nongnu.org; Sun, 07 Dec 2008 14:39:59 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1L9PTy-0002Uv-TY for qemu-devel@nongnu.org; Sun, 07 Dec 2008 19:39:59 +0000 Received: from balrog by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1L9PTy-0002Uh-GH for qemu-devel@nongnu.org; Sun, 07 Dec 2008 19:39:58 +0000 MIME-Version: 1.0 Errors-To: balrog Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Andrzej Zaborowski Message-Id: Date: Sun, 07 Dec 2008 19:39:58 +0000 Subject: [Qemu-devel] [5935] SH4: Eliminate P4 to A7 mangling (Takashi YOSHII). Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5935 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5935 Author: balrog Date: 2008-12-07 19:39:58 +0000 (Sun, 07 Dec 2008) Log Message: ----------- SH4: Eliminate P4 to A7 mangling (Takashi YOSHII). Main purpose of this is to delete *physical = address & 0x1fffffff; at target-sh4/helper.c:449, using new mmio rule introduced by #5849 This masking is a nice trick to realize P4/A7 duality of SH registers. But, IMHO, it is logically wrong. Most of SH4 cpu control registers in P4 area(0xfc000000...0xffffffff) have one more address called A7 which is usually P4 address with upper 3bits masked. This is an address only appears in TLB's physical address part. Current code use trick writing drivers as if they are really in A7 (that's why you see many *_A7 in hw/sh*.c), and using translation P4 to A7. Signed-off-by: Takashi YOSHII Signed-off-by: Andrzej Zaborowski Modified Paths: -------------- trunk/hw/sh.h trunk/hw/sh7750.c trunk/hw/sh_intc.c trunk/hw/sh_serial.c trunk/hw/sh_timer.c trunk/target-sh4/helper.c Modified: trunk/hw/sh.h =================================================================== --- trunk/hw/sh.h 2008-12-07 19:33:15 UTC (rev 5934) +++ trunk/hw/sh.h 2008-12-07 19:39:58 UTC (rev 5935) @@ -4,6 +4,9 @@ #include "sh_intc.h" +#define A7ADDR(x) ((x) & 0x1fffffff) +#define P4ADDR(x) ((x) | 0xe0000000) + /* sh7750.c */ struct SH7750State; Modified: trunk/hw/sh7750.c =================================================================== --- trunk/hw/sh7750.c 2008-12-07 19:33:15 UTC (rev 5934) +++ trunk/hw/sh7750.c 2008-12-07 19:39:58 UTC (rev 5935) @@ -683,10 +683,16 @@ sh7750_mem_write, s); cpu_register_physical_memory_offset(0x1f000000, 0x1000, sh7750_io_memory, 0x1f000000); + cpu_register_physical_memory_offset(0xff000000, 0x1000, + sh7750_io_memory, 0x1f000000); cpu_register_physical_memory_offset(0x1f800000, 0x1000, sh7750_io_memory, 0x1f800000); + cpu_register_physical_memory_offset(0xff800000, 0x1000, + sh7750_io_memory, 0x1f800000); cpu_register_physical_memory_offset(0x1fc00000, 0x1000, sh7750_io_memory, 0x1fc00000); + cpu_register_physical_memory_offset(0xffc00000, 0x1000, + sh7750_io_memory, 0x1fc00000); sh7750_mm_cache_and_tlb = cpu_register_io_memory(0, sh7750_mmct_read, Modified: trunk/hw/sh_intc.c =================================================================== --- trunk/hw/sh_intc.c 2008-12-07 19:33:15 UTC (rev 5934) +++ trunk/hw/sh_intc.c 2008-12-07 19:39:58 UTC (rev 5935) @@ -307,9 +307,12 @@ static void sh_intc_register(struct intc_desc *desc, unsigned long address) { - if (address) - cpu_register_physical_memory_offset(INTC_A7(address), 4, + if (address) { + cpu_register_physical_memory_offset(P4ADDR(address), 4, desc->iomemtype, INTC_A7(address)); + cpu_register_physical_memory_offset(A7ADDR(address), 4, + desc->iomemtype, INTC_A7(address)); + } } static void sh_intc_register_source(struct intc_desc *desc, Modified: trunk/hw/sh_serial.c =================================================================== --- trunk/hw/sh_serial.c 2008-12-07 19:33:15 UTC (rev 5934) +++ trunk/hw/sh_serial.c 2008-12-07 19:39:58 UTC (rev 5935) @@ -399,7 +399,8 @@ s_io_memory = cpu_register_io_memory(0, sh_serial_readfn, sh_serial_writefn, s); - cpu_register_physical_memory(base, 0x28, s_io_memory); + cpu_register_physical_memory(P4ADDR(base), 0x28, s_io_memory); + cpu_register_physical_memory(A7ADDR(base), 0x28, s_io_memory); s->chr = chr; Modified: trunk/hw/sh_timer.c =================================================================== --- trunk/hw/sh_timer.c 2008-12-07 19:33:15 UTC (rev 5934) +++ trunk/hw/sh_timer.c 2008-12-07 19:39:58 UTC (rev 5935) @@ -320,6 +320,7 @@ ch2_irq0); /* ch2_irq1 not supported */ iomemtype = cpu_register_io_memory(0, tmu012_readfn, tmu012_writefn, s); - cpu_register_physical_memory(base, 0x00001000, iomemtype); + cpu_register_physical_memory(P4ADDR(base), 0x00001000, iomemtype); + cpu_register_physical_memory(A7ADDR(base), 0x00001000, iomemtype); /* ??? Save/restore. */ } Modified: trunk/target-sh4/helper.c =================================================================== --- trunk/target-sh4/helper.c 2008-12-07 19:33:15 UTC (rev 5934) +++ trunk/target-sh4/helper.c 2008-12-07 19:39:58 UTC (rev 5935) @@ -439,19 +439,7 @@ if (address >= 0x80000000 && address < 0xc0000000) { /* Mask upper 3 bits for P1 and P2 areas */ *physical = address & 0x1fffffff; - } else if (address >= 0xfd000000 && address < 0xfe000000) { - /* PCI memory space */ - *physical = address; - } else if (address >= 0xfc000000) { - /* - * Mask upper 3 bits for control registers in P4 area, - * to unify access to control registers via P0-P3 area. - * The addresses for cache store queue, TLB address array - * are not masked. - */ - *physical = address & 0x1fffffff; } else { - /* access to cache store queue, or TLB address array. */ *physical = address; } *prot = PAGE_READ | PAGE_WRITE;