From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LCMPl-0007Y9-Su for qemu-devel@nongnu.org; Mon, 15 Dec 2008 17:59:49 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LCMPl-0007XN-5Z for qemu-devel@nongnu.org; Mon, 15 Dec 2008 17:59:49 -0500 Received: from [199.232.76.173] (port=48411 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LCMPl-0007Wo-2C for qemu-devel@nongnu.org; Mon, 15 Dec 2008 17:59:49 -0500 Received: from savannah.gnu.org ([199.232.41.3]:35711 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LCMPj-0007hE-Sd for qemu-devel@nongnu.org; Mon, 15 Dec 2008 17:59:48 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1LCMPi-0002VN-6s for qemu-devel@nongnu.org; Mon, 15 Dec 2008 22:59:46 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1LCMPh-0002VJ-Vn for qemu-devel@nongnu.org; Mon, 15 Dec 2008 22:59:46 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Mon, 15 Dec 2008 22:59:45 +0000 Subject: [Qemu-devel] [6062] target-ppc: rename ppc405_sdram_init() to ppc4xx_sdram_init() Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 6062 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6062 Author: aurel32 Date: 2008-12-15 22:59:45 +0000 (Mon, 15 Dec 2008) Log Message: ----------- target-ppc: rename ppc405_sdram_init() to ppc4xx_sdram_init() The SDRAM controller is shared across almost all 405 and 440 embedded processors, with some slight differences such as the sizes supported for each memory bank. Rename only; no functional changes. Signed-off-by: Hollis Blanchard Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/hw/ppc405_uc.c trunk/hw/ppc4xx.h trunk/hw/ppc4xx_devs.c Modified: trunk/hw/ppc405_uc.c =================================================================== --- trunk/hw/ppc405_uc.c 2008-12-15 22:59:34 UTC (rev 6061) +++ trunk/hw/ppc405_uc.c 2008-12-15 22:59:45 UTC (rev 6062) @@ -2230,7 +2230,7 @@ pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); *picp = pic; /* SDRAM controller */ - ppc405_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); + ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); offset = 0; for (i = 0; i < 4; i++) offset += ram_sizes[i]; @@ -2588,7 +2588,7 @@ *picp = pic; /* SDRAM controller */ /* XXX 405EP has no ECC interrupt */ - ppc405_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); + ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); offset = 0; for (i = 0; i < 2; i++) offset += ram_sizes[i]; Modified: trunk/hw/ppc4xx.h =================================================================== --- trunk/hw/ppc4xx.h 2008-12-15 22:59:34 UTC (rev 6061) +++ trunk/hw/ppc4xx.h 2008-12-15 22:59:45 UTC (rev 6062) @@ -48,7 +48,7 @@ qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, uint32_t dcr_base, int has_ssr, int has_vr); -void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks, +void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, target_phys_addr_t *ram_bases, target_phys_addr_t *ram_sizes, int do_init); Modified: trunk/hw/ppc4xx_devs.c =================================================================== --- trunk/hw/ppc4xx_devs.c 2008-12-15 22:59:34 UTC (rev 6061) +++ trunk/hw/ppc4xx_devs.c 2008-12-15 22:59:45 UTC (rev 6062) @@ -846,7 +846,7 @@ sdram_unmap_bcr(sdram); } -void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks, +void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, target_phys_addr_t *ram_bases, target_phys_addr_t *ram_sizes, int do_init)