From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [6087] target-ppc: add Altivec logical operations
Date: Thu, 18 Dec 2008 22:42:59 +0000 [thread overview]
Message-ID: <E1LDRa7-0002Mz-2q@cvs.savannah.gnu.org> (raw)
Revision: 6087
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6087
Author: aurel32
Date: 2008-12-18 22:42:58 +0000 (Thu, 18 Dec 2008)
Log Message:
-----------
target-ppc: add Altivec logical operations
Use opc2/opc3 instead of one big xo field. Do this consistency with the
rest of translate.c
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Modified Paths:
--------------
trunk/target-ppc/translate.c
Modified: trunk/target-ppc/translate.c
===================================================================
--- trunk/target-ppc/translate.c 2008-12-18 22:42:51 UTC (rev 6086)
+++ trunk/target-ppc/translate.c 2008-12-18 22:42:58 UTC (rev 6087)
@@ -6139,6 +6139,24 @@
/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
GEN_VR_STX(svxl, 0x07, 0x0F);
+/* Logical operations */
+#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
+GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
+{ \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
+ tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
+}
+
+GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
+GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
+GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
+GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
+GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
+
/*** SPE extension ***/
/* Register moves */
reply other threads:[~2008-12-18 22:43 UTC|newest]
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