From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LDRah-0000Lm-Ne for qemu-devel@nongnu.org; Thu, 18 Dec 2008 17:43:35 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LDRag-0000LD-Um for qemu-devel@nongnu.org; Thu, 18 Dec 2008 17:43:35 -0500 Received: from [199.232.76.173] (port=59873 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LDRag-0000L3-O0 for qemu-devel@nongnu.org; Thu, 18 Dec 2008 17:43:34 -0500 Received: from savannah.gnu.org ([199.232.41.3]:43679 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LDRag-00084H-BU for qemu-devel@nongnu.org; Thu, 18 Dec 2008 17:43:34 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1LDRaf-0002Ql-PC for qemu-devel@nongnu.org; Thu, 18 Dec 2008 22:43:33 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1LDRaf-0002Qc-Jn for qemu-devel@nongnu.org; Thu, 18 Dec 2008 22:43:33 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Thu, 18 Dec 2008 22:43:33 +0000 Subject: [Qemu-devel] [6091] PCI: Mask writes to RO bits in the status reg of PCI config space Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 6091 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6091 Author: aurel32 Date: 2008-12-18 22:43:33 +0000 (Thu, 18 Dec 2008) Log Message: ----------- PCI: Mask writes to RO bits in the status reg of PCI config space The Status register in the PCI config space has some read-only bits. Any writes to those bits should be masked out. Signed-off-by: Amit Shah Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/hw/pci.c trunk/hw/pci.h Modified: trunk/hw/pci.c =================================================================== --- trunk/hw/pci.c 2008-12-18 22:43:25 UTC (rev 6090) +++ trunk/hw/pci.c 2008-12-18 22:43:33 UTC (rev 6091) @@ -381,6 +381,7 @@ case 0x0b: case 0x0e: case 0x10 ... 0x27: /* base */ + case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ case 0x30 ... 0x33: /* rom */ case 0x3d: can_write = 0; @@ -402,6 +403,7 @@ case 0x0a: case 0x0b: case 0x0e: + case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ case 0x38 ... 0x3b: /* rom */ case 0x3d: can_write = 0; @@ -413,6 +415,15 @@ break; } if (can_write) { + /* Mask out writes to reserved bits in registers */ + switch (addr) { + case 0x06: + val &= ~PCI_STATUS_RESERVED_MASK_LO; + break; + case 0x07: + val &= ~PCI_STATUS_RESERVED_MASK_HI; + break; + } d->config[addr] = val; } if (++addr > 0xff) Modified: trunk/hw/pci.h =================================================================== --- trunk/hw/pci.h 2008-12-18 22:43:25 UTC (rev 6090) +++ trunk/hw/pci.h 2008-12-18 22:43:33 UTC (rev 6091) @@ -54,6 +54,21 @@ #define PCI_MIN_GNT 0x3e /* 8 bits */ #define PCI_MAX_LAT 0x3f /* 8 bits */ +/* Bits in the PCI Status Register (PCI 2.3 spec) */ +#define PCI_STATUS_RESERVED1 0x007 +#define PCI_STATUS_INT_STATUS 0x008 +#define PCI_STATUS_CAPABILITIES 0x010 +#define PCI_STATUS_66MHZ 0x020 +#define PCI_STATUS_RESERVED2 0x040 +#define PCI_STATUS_FAST_BACK 0x080 +#define PCI_STATUS_DEVSEL 0x600 + +#define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \ + PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \ + PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK) + +#define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8) + struct PCIDevice { /* PCI config space */ uint8_t config[256];