From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LDfFa-0004Gi-Uz for qemu-devel@nongnu.org; Fri, 19 Dec 2008 08:18:42 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LDfFZ-0004GW-Ef for qemu-devel@nongnu.org; Fri, 19 Dec 2008 08:18:41 -0500 Received: from [199.232.76.173] (port=43636 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LDfFZ-0004GM-7m for qemu-devel@nongnu.org; Fri, 19 Dec 2008 08:18:41 -0500 Received: from savannah.gnu.org ([199.232.41.3]:42798 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LDfFY-0007bu-74 for qemu-devel@nongnu.org; Fri, 19 Dec 2008 08:18:40 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1LDfFW-0003ZH-GD for qemu-devel@nongnu.org; Fri, 19 Dec 2008 13:18:39 +0000 Received: from pbrook by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1LDfFV-0003Z4-Kg for qemu-devel@nongnu.org; Fri, 19 Dec 2008 13:18:38 +0000 MIME-Version: 1.0 Errors-To: pbrook Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Paul Brook Message-Id: Date: Fri, 19 Dec 2008 13:18:37 +0000 Subject: [Qemu-devel] [6104] Implement (very) basic Thumb2-EE support. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 6104 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6104 Author: pbrook Date: 2008-12-19 13:18:36 +0000 (Fri, 19 Dec 2008) Log Message: ----------- Implement (very) basic Thumb2-EE support. This doesn't actually implement EE state, just the associated system coprocessor registers. It is sufficient to keep OS setup and context switching code happy. Signed-off-by: Paul Brook Modified Paths: -------------- trunk/target-arm/cpu.h trunk/target-arm/helper.c trunk/target-arm/helpers.h trunk/target-arm/translate.c Modified: trunk/target-arm/cpu.h =================================================================== --- trunk/target-arm/cpu.h 2008-12-19 13:02:08 UTC (rev 6103) +++ trunk/target-arm/cpu.h 2008-12-19 13:18:36 UTC (rev 6104) @@ -151,6 +151,10 @@ void *opaque; } cp[15]; + /* Thumb-2 EE state. */ + uint32_t teecr; + uint32_t teehbr; + /* Internal CPU feature flags. */ uint32_t features; @@ -329,7 +333,8 @@ ARM_FEATURE_NEON, ARM_FEATURE_DIV, ARM_FEATURE_M, /* Microcontroller profile. */ - ARM_FEATURE_OMAPCP /* OMAP specific CP15 ops handling. */ + ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ + ARM_FEATURE_THUMB2EE }; static inline int arm_feature(CPUARMState *env, int feature) Modified: trunk/target-arm/helper.c =================================================================== --- trunk/target-arm/helper.c 2008-12-19 13:02:08 UTC (rev 6103) +++ trunk/target-arm/helper.c 2008-12-19 13:18:36 UTC (rev 6104) @@ -88,6 +88,7 @@ set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_VFP3); set_feature(env, ARM_FEATURE_NEON); + set_feature(env, ARM_FEATURE_THUMB2EE); env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100; @@ -110,6 +111,7 @@ set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_VFP3); set_feature(env, ARM_FEATURE_NEON); + set_feature(env, ARM_FEATURE_THUMB2EE); set_feature(env, ARM_FEATURE_DIV); break; case ARM_CPUID_TI915T: @@ -2595,3 +2597,12 @@ tmp = float32_scalbn(tmp, 31, s); return float32_to_int32(tmp, s); } + +void HELPER(set_teecr)(CPUState *env, uint32_t val) +{ + val &= 1; + if (env->teecr != val) { + env->teecr = val; + tb_flush(env); + } +} Modified: trunk/target-arm/helpers.h =================================================================== --- trunk/target-arm/helpers.h 2008-12-19 13:02:08 UTC (rev 6103) +++ trunk/target-arm/helpers.h 2008-12-19 13:18:36 UTC (rev 6104) @@ -453,4 +453,6 @@ DEF_HELPER_3(iwmmxt_muladdsw, i64, i64, i32, i32) DEF_HELPER_3(iwmmxt_muladdswl, i64, i64, i32, i32) +DEF_HELPER_2(set_teecr, void, env, i32) + #include "def-helper.h" Modified: trunk/target-arm/translate.c =================================================================== --- trunk/target-arm/translate.c 2008-12-19 13:02:08 UTC (rev 6103) +++ trunk/target-arm/translate.c 2008-12-19 13:18:36 UTC (rev 6104) @@ -5536,6 +5536,71 @@ return 0; } +static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn) +{ + int crn = (insn >> 16) & 0xf; + int crm = insn & 0xf; + int op1 = (insn >> 21) & 7; + int op2 = (insn >> 5) & 7; + int rt = (insn >> 12) & 0xf; + TCGv tmp; + + if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { + if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) { + /* TEECR */ + if (IS_USER(s)) + return 1; + tmp = load_cpu_field(teecr); + store_reg(s, rt, tmp); + return 0; + } + if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) { + /* TEEHBR */ + if (IS_USER(s) && (env->teecr & 1)) + return 1; + tmp = load_cpu_field(teehbr); + store_reg(s, rt, tmp); + return 0; + } + } + fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n", + op1, crn, crm, op2); + return 1; +} + +static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn) +{ + int crn = (insn >> 16) & 0xf; + int crm = insn & 0xf; + int op1 = (insn >> 21) & 7; + int op2 = (insn >> 5) & 7; + int rt = (insn >> 12) & 0xf; + TCGv tmp; + + if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { + if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) { + /* TEECR */ + if (IS_USER(s)) + return 1; + tmp = load_reg(s, rt); + gen_helper_set_teecr(cpu_env, tmp); + dead_tmp(tmp); + return 0; + } + if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) { + /* TEEHBR */ + if (IS_USER(s) && (env->teecr & 1)) + return 1; + tmp = load_reg(s, rt); + store_cpu_field(tmp, teehbr); + return 0; + } + } + fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n", + op1, crn, crm, op2); + return 1; +} + static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn) { int cpnum; @@ -5557,9 +5622,19 @@ case 10: case 11: return disas_vfp_insn (env, s, insn); + case 14: + /* Coprocessors 7-15 are architecturally reserved by ARM. + Unfortunately Intel decided to ignore this. */ + if (arm_feature(env, ARM_FEATURE_XSCALE)) + goto board; + if (insn & (1 << 20)) + return disas_cp14_read(env, s, insn); + else + return disas_cp14_write(env, s, insn); case 15: return disas_cp15_insn (env, s, insn); default: + board: /* Unknown coprocessor. See if the board has hooked it. */ return disas_cp_insn (env, s, insn); }