From: Paul Brook <paul@nowt.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [6105] Implement ARMv7 cp15 cache ID registers.
Date: Fri, 19 Dec 2008 13:37:53 +0000 [thread overview]
Message-ID: <E1LDfY9-0004Wd-ML@cvs.savannah.gnu.org> (raw)
Revision: 6105
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6105
Author: pbrook
Date: 2008-12-19 13:37:53 +0000 (Fri, 19 Dec 2008)
Log Message:
-----------
Implement ARMv7 cp15 cache ID registers.
Modified Paths:
--------------
trunk/target-arm/cpu.h
trunk/target-arm/helper.c
Modified: trunk/target-arm/cpu.h
===================================================================
--- trunk/target-arm/cpu.h 2008-12-19 13:18:36 UTC (rev 6104)
+++ trunk/target-arm/cpu.h 2008-12-19 13:37:53 UTC (rev 6105)
@@ -100,6 +100,9 @@
struct {
uint32_t c0_cpuid;
uint32_t c0_cachetype;
+ uint32_t c0_ccsid[16]; /* Cache size. */
+ uint32_t c0_clid; /* Cache level. */
+ uint32_t c0_cssel; /* Cache size selection. */
uint32_t c0_c1[8]; /* Feature registers. */
uint32_t c0_c2[8]; /* Instruction set registers. */
uint32_t c1_sys; /* System control register. */
Modified: trunk/target-arm/helper.c
===================================================================
--- trunk/target-arm/helper.c 2008-12-19 13:18:36 UTC (rev 6104)
+++ trunk/target-arm/helper.c 2008-12-19 13:37:53 UTC (rev 6105)
@@ -94,7 +94,11 @@
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
- env->cp15.c0_cachetype = 0x1dd20d2;
+ env->cp15.c0_cachetype = 0x82048004;
+ env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
+ env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
+ env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
+ env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
break;
case ARM_CPUID_CORTEXM3:
set_feature(env, ARM_FEATURE_V6);
@@ -1321,15 +1325,16 @@
crm = insn & 0xf;
switch ((insn >> 16) & 0xf) {
case 0:
- if (((insn >> 21) & 7) == 2) {
- /* ??? Select cache level. Ignore. */
- return;
- }
/* ID codes. */
if (arm_feature(env, ARM_FEATURE_XSCALE))
break;
if (arm_feature(env, ARM_FEATURE_OMAPCP))
break;
+ if (arm_feature(env, ARM_FEATURE_V7)
+ && op1 == 2 && crm == 0 && op2 == 0) {
+ env->cp15.c0_cssel = val & 0xf;
+ break;
+ }
goto bad_reg;
case 1: /* System configuration. */
if (arm_feature(env, ARM_FEATURE_OMAPCP))
@@ -1648,9 +1653,22 @@
goto bad_reg;
if (crm != 0)
goto bad_reg;
- if (arm_feature(env, ARM_FEATURE_XSCALE))
+ if (!arm_feature(env, ARM_FEATURE_V7))
+ return 0;
+
+ switch (op2) {
+ case 0:
+ return env->cp15.c0_ccsid[env->cp15.c0_cssel];
+ case 1:
+ return env->cp15.c0_clid;
+ case 7:
+ return 0;
+ }
+ goto bad_reg;
+ case 2:
+ if (op2 != 0 || crm != 0)
goto bad_reg;
- return 0;
+ return env->cp15.c0_cssel;
default:
goto bad_reg;
}
reply other threads:[~2008-12-19 13:37 UTC|newest]
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