From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [6172] Add GEN_VXFORM_SIMM macro for subsequent instructions.
Date: Sun, 04 Jan 2009 22:10:29 +0000 [thread overview]
Message-ID: <E1LJbAz-0001yu-2u@cvs.savannah.gnu.org> (raw)
Revision: 6172
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6172
Author: aurel32
Date: 2009-01-04 22:10:28 +0000 (Sun, 04 Jan 2009)
Log Message:
-----------
Add GEN_VXFORM_SIMM macro for subsequent instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Modified Paths:
--------------
trunk/target-ppc/translate.c
Modified: trunk/target-ppc/translate.c
===================================================================
--- trunk/target-ppc/translate.c 2009-01-04 22:10:09 UTC (rev 6171)
+++ trunk/target-ppc/translate.c 2009-01-04 22:10:28 UTC (rev 6172)
@@ -370,6 +370,8 @@
EXTRACT_SHELPER(SIMM, 0, 16);
/* 16 bits unsigned immediate value */
EXTRACT_HELPER(UIMM, 0, 16);
+/* 5 bits signed immediate value */
+EXTRACT_HELPER(SIMM5, 16, 5);
/* Bit count */
EXTRACT_HELPER(NB, 11, 5);
/* Shift count */
@@ -6270,6 +6272,22 @@
GEN_VXFORM(vrlh, 2, 1);
GEN_VXFORM(vrlw, 2, 2);
+#define GEN_VXFORM_SIMM(name, opc2, opc3) \
+ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
+ { \
+ TCGv_ptr rd; \
+ TCGv_i32 simm; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ simm = tcg_const_i32(SIMM5(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##name (rd, simm); \
+ tcg_temp_free_i32(simm); \
+ tcg_temp_free_ptr(rd); \
+ }
+
GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
{
TCGv_ptr ra, rb, rd;
reply other threads:[~2009-01-04 22:10 UTC|newest]
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