From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [6275] target-ppc: add altivec cache instructions
Date: Mon, 12 Jan 2009 21:33:03 +0000 [thread overview]
Message-ID: <E1LMUP9-0003DV-8u@cvs.savannah.gnu.org> (raw)
Revision: 6275
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6275
Author: aurel32
Date: 2009-01-12 21:33:02 +0000 (Mon, 12 Jan 2009)
Log Message:
-----------
target-ppc: add altivec cache instructions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Modified Paths:
--------------
trunk/target-ppc/translate.c
Modified: trunk/target-ppc/translate.c
===================================================================
--- trunk/target-ppc/translate.c 2009-01-12 21:12:22 UTC (rev 6274)
+++ trunk/target-ppc/translate.c 2009-01-12 21:33:02 UTC (rev 6275)
@@ -4152,6 +4152,33 @@
tcg_temp_free(t0);
}
+/* dst / dstt */
+GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC)
+{
+ if (rA(ctx->opcode) == 0) {
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
+ } else {
+ /* interpreted as no-op */
+ }
+}
+
+/* dstst /dststt */
+GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC)
+{
+ if (rA(ctx->opcode) == 0) {
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
+ } else {
+ /* interpreted as no-op */
+ }
+
+}
+
+/* dss / dssall */
+GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC)
+{
+ /* interpreted as no-op */
+}
+
/* icbi */
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
{
reply other threads:[~2009-01-12 21:33 UTC|newest]
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