From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LOeh7-0002iI-N0 for qemu-devel@nongnu.org; Sun, 18 Jan 2009 15:56:33 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LOeh6-0002i3-4W for qemu-devel@nongnu.org; Sun, 18 Jan 2009 15:56:32 -0500 Received: from [199.232.76.173] (port=60272 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LOeh5-0002hw-WB for qemu-devel@nongnu.org; Sun, 18 Jan 2009 15:56:32 -0500 Received: from savannah.gnu.org ([199.232.41.3]:40916 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LOeh5-0001Js-JA for qemu-devel@nongnu.org; Sun, 18 Jan 2009 15:56:31 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1LOeh5-0001cm-31 for qemu-devel@nongnu.org; Sun, 18 Jan 2009 20:56:31 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1LOeh4-0001ci-Rd for qemu-devel@nongnu.org; Sun, 18 Jan 2009 20:56:31 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Sun, 18 Jan 2009 20:56:30 +0000 Subject: [Qemu-devel] [6368] USB OHCI: add support for big endian targets Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 6368 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6368 Author: aurel32 Date: 2009-01-18 20:56:30 +0000 (Sun, 18 Jan 2009) Log Message: ----------- USB OHCI: add support for big endian targets Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/hw/usb-ohci.c Modified: trunk/hw/usb-ohci.c =================================================================== --- trunk/hw/usb-ohci.c 2009-01-18 14:28:20 UTC (rev 6367) +++ trunk/hw/usb-ohci.c 2009-01-18 20:56:30 UTC (rev 6368) @@ -1360,103 +1360,135 @@ static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr) { OHCIState *ohci = ptr; + uint32_t retval; /* Only aligned reads are allowed on OHCI */ if (addr & 3) { fprintf(stderr, "usb-ohci: Mis-aligned read\n"); return 0xffffffff; - } - - if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { + } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { /* HcRhPortStatus */ - return ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS; - } + retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS; + } else { + switch (addr >> 2) { + case 0: /* HcRevision */ + retval = 0x10; + break; - switch (addr >> 2) { - case 0: /* HcRevision */ - return 0x10; + case 1: /* HcControl */ + retval = ohci->ctl; + break; - case 1: /* HcControl */ - return ohci->ctl; + case 2: /* HcCommandStatus */ + retval = ohci->status; + break; - case 2: /* HcCommandStatus */ - return ohci->status; + case 3: /* HcInterruptStatus */ + retval = ohci->intr_status; + break; - case 3: /* HcInterruptStatus */ - return ohci->intr_status; + case 4: /* HcInterruptEnable */ + case 5: /* HcInterruptDisable */ + retval = ohci->intr; + break; - case 4: /* HcInterruptEnable */ - case 5: /* HcInterruptDisable */ - return ohci->intr; + case 6: /* HcHCCA */ + retval = ohci->hcca; + break; - case 6: /* HcHCCA */ - return ohci->hcca; + case 7: /* HcPeriodCurrentED */ + retval = ohci->per_cur; + break; - case 7: /* HcPeriodCurrentED */ - return ohci->per_cur; + case 8: /* HcControlHeadED */ + retval = ohci->ctrl_head; + break; - case 8: /* HcControlHeadED */ - return ohci->ctrl_head; + case 9: /* HcControlCurrentED */ + retval = ohci->ctrl_cur; + break; - case 9: /* HcControlCurrentED */ - return ohci->ctrl_cur; + case 10: /* HcBulkHeadED */ + retval = ohci->bulk_head; + break; - case 10: /* HcBulkHeadED */ - return ohci->bulk_head; + case 11: /* HcBulkCurrentED */ + retval = ohci->bulk_cur; + break; - case 11: /* HcBulkCurrentED */ - return ohci->bulk_cur; + case 12: /* HcDoneHead */ + retval = ohci->done; + break; - case 12: /* HcDoneHead */ - return ohci->done; + case 13: /* HcFmInterretval */ + retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi); + break; - case 13: /* HcFmInterval */ - return (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi); + case 14: /* HcFmRemaining */ + retval = ohci_get_frame_remaining(ohci); + break; - case 14: /* HcFmRemaining */ - return ohci_get_frame_remaining(ohci); + case 15: /* HcFmNumber */ + retval = ohci->frame_number; + break; - case 15: /* HcFmNumber */ - return ohci->frame_number; + case 16: /* HcPeriodicStart */ + retval = ohci->pstart; + break; - case 16: /* HcPeriodicStart */ - return ohci->pstart; + case 17: /* HcLSThreshold */ + retval = ohci->lst; + break; - case 17: /* HcLSThreshold */ - return ohci->lst; + case 18: /* HcRhDescriptorA */ + retval = ohci->rhdesc_a; + break; - case 18: /* HcRhDescriptorA */ - return ohci->rhdesc_a; + case 19: /* HcRhDescriptorB */ + retval = ohci->rhdesc_b; + break; - case 19: /* HcRhDescriptorB */ - return ohci->rhdesc_b; + case 20: /* HcRhStatus */ + retval = ohci->rhstatus; + break; - case 20: /* HcRhStatus */ - return ohci->rhstatus; + /* PXA27x specific registers */ + case 24: /* HcStatus */ + retval = ohci->hstatus & ohci->hmask; + break; - /* PXA27x specific registers */ - case 24: /* HcStatus */ - return ohci->hstatus & ohci->hmask; + case 25: /* HcHReset */ + retval = ohci->hreset; + break; - case 25: /* HcHReset */ - return ohci->hreset; + case 26: /* HcHInterruptEnable */ + retval = ohci->hmask; + break; - case 26: /* HcHInterruptEnable */ - return ohci->hmask; + case 27: /* HcHInterruptTest */ + retval = ohci->htest; + break; - case 27: /* HcHInterruptTest */ - return ohci->htest; + default: + fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr); + retval = 0xffffffff; + } + } - default: - fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr); - return 0xffffffff; - } +#ifdef TARGET_WORDS_BIGENDIAN + retval = bswap32(retval); +#endif + return retval; } static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val) { OHCIState *ohci = ptr; +#ifdef TARGET_WORDS_BIGENDIAN + val = bswap32(val); +#endif + /* Only aligned reads are allowed on OHCI */ if (addr & 3) { fprintf(stderr, "usb-ohci: Mis-aligned write\n");