From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LQk7P-0005lX-Ee for qemu-devel@nongnu.org; Sat, 24 Jan 2009 10:08:19 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LQk7O-0005lL-VD for qemu-devel@nongnu.org; Sat, 24 Jan 2009 10:08:19 -0500 Received: from [199.232.76.173] (port=39412 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LQk7O-0005lI-RT for qemu-devel@nongnu.org; Sat, 24 Jan 2009 10:08:18 -0500 Received: from savannah.gnu.org ([199.232.41.3]:42741 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LQk7O-0004QN-EZ for qemu-devel@nongnu.org; Sat, 24 Jan 2009 10:08:18 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1LQk7O-0000Ul-2o for qemu-devel@nongnu.org; Sat, 24 Jan 2009 15:08:18 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1LQk7N-0000Uf-N6 for qemu-devel@nongnu.org; Sat, 24 Jan 2009 15:08:17 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Sat, 24 Jan 2009 15:08:17 +0000 Subject: [Qemu-devel] [6425] target-ppc: Add SPE register read/write using XML Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 6425 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6425 Author: aurel32 Date: 2009-01-24 15:08:17 +0000 (Sat, 24 Jan 2009) Log Message: ----------- target-ppc: Add SPE register read/write using XML Don't read/write SPEFSCR until we figure out what to do about exceptions. Signed-off-by: Nathan Froyd Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/target-ppc/translate_init.c Modified: trunk/target-ppc/translate_init.c =================================================================== --- trunk/target-ppc/translate_init.c 2009-01-24 15:08:09 UTC (rev 6424) +++ trunk/target-ppc/translate_init.c 2009-01-24 15:08:17 UTC (rev 6425) @@ -9345,6 +9345,51 @@ return 0; } +static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { +#if defined(TARGET_PPC64) + stl_p(mem_buf, env->gpr[n] >> 32); +#else + stl_p(mem_buf, env->gprh[n]); +#endif + return 4; + } + if (n == 33) { + stq_p(mem_buf, env->spe_acc); + return 8; + } + if (n == 34) { + /* SPEFSCR not implemented */ + memset(mem_buf, 0, 4); + return 4; + } + return 0; +} + +static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { +#if defined(TARGET_PPC64) + target_ulong lo = (uint32_t)env->gpr[n]; + target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32; + env->gpr[n] = lo | hi; +#else + env->gprh[n] = ldl_p(mem_buf); +#endif + return 4; + } + if (n == 33) { + env->spe_acc = ldq_p(mem_buf); + return 8; + } + if (n == 34) { + /* SPEFSCR not implemented */ + return 4; + } + return 0; +} + int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def) { env->msr_mask = def->msr_mask; @@ -9366,6 +9411,11 @@ gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg, 34, "power-altivec.xml", 0); } + if ((def->insns_flags & PPC_SPE) | (def->insns_flags & PPC_SPEFPU)) { + gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg, + 34, "power-spe.xml", 0); + } + #if defined(PPC_DUMP_CPU) { const char *mmu_model, *excp_model, *bus_model;