[Qemu-devel] [6433] sh4: sh_pci.

[Qemu-devel] [6433] sh4: sh_pci.

[Aurelien Jarno]

Revision: 6433
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6433
Author:   aurel32
Date:     2009-01-24 18:21:08 +0000 (Sat, 24 Jan 2009)

Log Message:
-----------
sh4: sh_pci. Register resouces both at A7 and P4.

Add resource registration both for P4 and A7.
This is needed because of #5935 SH4: Eliminate P4 to A7 mangling.
Additionally, {reg,iop,mem}base which is no longer used are removed.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

Modified Paths:
--------------
    trunk/hw/sh_pci.c

Modified: trunk/hw/sh_pci.c
===================================================================
--- trunk/hw/sh_pci.c	2009-01-24 18:19:25 UTC (rev 6432)
+++ trunk/hw/sh_pci.c	2009-01-24 18:21:08 UTC (rev 6433)
@@ -29,9 +29,6 @@
 typedef struct {
     PCIBus *bus;
     PCIDevice *dev;
-    uint32_t regbase;
-    uint32_t iopbase;
-    uint32_t membase;
     uint32_t par;
     uint32_t mbr;
     uint32_t iobr;
@@ -181,15 +178,15 @@
 
     p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),
                                  -1, NULL, NULL);
-    p->regbase = 0x1e200000;
-    p->iopbase = 0x1e240000;
-    p->membase = 0xfd000000;
     reg = cpu_register_io_memory(0, sh_pci_reg.r, sh_pci_reg.w, p);
-    mem = cpu_register_io_memory(0, sh_pci_mem.r, sh_pci_mem.w, p);
     iop = cpu_register_io_memory(0, sh_pci_iop.r, sh_pci_iop.w, p);
-    cpu_register_physical_memory(p->regbase, 0x224, reg);
-    cpu_register_physical_memory(p->iopbase, 0x40000, iop);
-    cpu_register_physical_memory(p->membase, 0x1000000, mem);
+    mem = cpu_register_io_memory(0, sh_pci_mem.r, sh_pci_mem.w, p);
+    cpu_register_physical_memory(0x1e200000, 0x224, reg);
+    cpu_register_physical_memory(0x1e240000, 0x40000, iop);
+    cpu_register_physical_memory(0x1d000000, 0x1000000, mem);
+    cpu_register_physical_memory(0xfe200000, 0x224, reg);
+    cpu_register_physical_memory(0xfe240000, 0x40000, iop);
+    cpu_register_physical_memory(0xfd000000, 0x1000000, mem);
 
     p->dev->config[0x00] = 0x54; // HITACHI
     p->dev->config[0x01] = 0x10; //