From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LU2Jz-0005ND-82 for qemu-devel@nongnu.org; Mon, 02 Feb 2009 12:10:55 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LU2Jy-0005Lh-IZ for qemu-devel@nongnu.org; Mon, 02 Feb 2009 12:10:54 -0500 Received: from [199.232.76.173] (port=55070 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LU2Jy-0005LN-9U for qemu-devel@nongnu.org; Mon, 02 Feb 2009 12:10:54 -0500 Received: from savannah.gnu.org ([199.232.41.3]:39516 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LU2Jy-0000on-2d for qemu-devel@nongnu.org; Mon, 02 Feb 2009 12:10:54 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1LU2Jx-0002Fc-I1 for qemu-devel@nongnu.org; Mon, 02 Feb 2009 17:10:53 +0000 Received: from aliguori by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1LU2Jx-0002FM-5P for qemu-devel@nongnu.org; Mon, 02 Feb 2009 17:10:53 +0000 MIME-Version: 1.0 Errors-To: aliguori Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Anthony Liguori Message-Id: Date: Mon, 02 Feb 2009 17:10:53 +0000 Subject: [Qemu-devel] [6500] Implement FFXSR (Alexander Graf) Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 6500 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6500 Author: aliguori Date: 2009-02-02 17:10:52 +0000 (Mon, 02 Feb 2009) Log Message: ----------- Implement FFXSR (Alexander Graf) Newer AMD CPUs have the FFXSR capability. This leaves out XMM register in FXSAVE/FXRESTORE when in CPL=0 and 64-bit mode. This is required for Hyper-V. Signed-off-by: Alexander Graf Signed-off-by: Anthony Liguori Modified Paths: -------------- trunk/target-i386/op_helper.c Modified: trunk/target-i386/op_helper.c =================================================================== --- trunk/target-i386/op_helper.c 2009-02-02 15:58:54 UTC (rev 6499) +++ trunk/target-i386/op_helper.c 2009-02-02 17:10:52 UTC (rev 6500) @@ -3030,6 +3030,8 @@ update_mask |= MSR_EFER_NXE; if (env->cpuid_ext3_features & CPUID_EXT3_SVM) update_mask |= MSR_EFER_SVME; + if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR) + update_mask |= MSR_EFER_FFXSR; cpu_load_efer(env, (env->efer & ~update_mask) | (val & update_mask)); } @@ -4352,10 +4354,15 @@ else nb_xmm_regs = 8; addr = ptr + 0xa0; - for(i = 0; i < nb_xmm_regs; i++) { - stq(addr, env->xmm_regs[i].XMM_Q(0)); - stq(addr + 8, env->xmm_regs[i].XMM_Q(1)); - addr += 16; + /* Fast FXSAVE leaves out the XMM registers */ + if (!(env->efer & MSR_EFER_FFXSR) + || (env->hflags & HF_CPL_MASK) + || !(env->hflags & HF_LMA_MASK)) { + for(i = 0; i < nb_xmm_regs; i++) { + stq(addr, env->xmm_regs[i].XMM_Q(0)); + stq(addr + 8, env->xmm_regs[i].XMM_Q(1)); + addr += 16; + } } } } @@ -4392,10 +4399,15 @@ else nb_xmm_regs = 8; addr = ptr + 0xa0; - for(i = 0; i < nb_xmm_regs; i++) { - env->xmm_regs[i].XMM_Q(0) = ldq(addr); - env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8); - addr += 16; + /* Fast FXRESTORE leaves out the XMM registers */ + if (!(env->efer & MSR_EFER_FFXSR) + || (env->hflags & HF_CPL_MASK) + || !(env->hflags & HF_LMA_MASK)) { + for(i = 0; i < nb_xmm_regs; i++) { + env->xmm_regs[i].XMM_Q(0) = ldq(addr); + env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8); + addr += 16; + } } } }