From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LURNF-0002W4-Em for qemu-devel@nongnu.org; Tue, 03 Feb 2009 14:55:57 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LURNE-0002VI-A8 for qemu-devel@nongnu.org; Tue, 03 Feb 2009 14:55:56 -0500 Received: from [199.232.76.173] (port=53346 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LURNE-0002V5-0s for qemu-devel@nongnu.org; Tue, 03 Feb 2009 14:55:56 -0500 Received: from savannah.gnu.org ([199.232.41.3]:59464 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LURNA-0006rI-Tf for qemu-devel@nongnu.org; Tue, 03 Feb 2009 14:55:53 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1LURNA-0001Xz-47 for qemu-devel@nongnu.org; Tue, 03 Feb 2009 19:55:52 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1LURN9-0001Xr-Qw for qemu-devel@nongnu.org; Tue, 03 Feb 2009 19:55:52 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Tue, 03 Feb 2009 19:55:51 +0000 Subject: [Qemu-devel] [6506] Rename spe_status to vec_status Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 6506 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6506 Author: aurel32 Date: 2009-02-03 19:55:51 +0000 (Tue, 03 Feb 2009) Log Message: ----------- Rename spe_status to vec_status Only one of Altivec and SPE will be available on a given chip. Signed-off-by: Nathan Froyd Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/target-ppc/cpu.h trunk/target-ppc/op_helper.c Modified: trunk/target-ppc/cpu.h =================================================================== --- trunk/target-ppc/cpu.h 2009-02-03 19:55:43 UTC (rev 6505) +++ trunk/target-ppc/cpu.h 2009-02-03 19:55:51 UTC (rev 6506) @@ -611,8 +611,10 @@ uint32_t vscr; /* SPE registers */ uint64_t spe_acc; - float_status spe_status; uint32_t spe_fscr; + /* SPE and Altivec can share a status since they will never be used + * simultaneously */ + float_status vec_status; /* Internal devices resources */ /* Time base and decrementer */ Modified: trunk/target-ppc/op_helper.c =================================================================== --- trunk/target-ppc/op_helper.c 2009-02-03 19:55:43 UTC (rev 6505) +++ trunk/target-ppc/op_helper.c 2009-02-03 19:55:51 UTC (rev 6506) @@ -2861,7 +2861,7 @@ { CPU_FloatU u; - u.f = int32_to_float32(val, &env->spe_status); + u.f = int32_to_float32(val, &env->vec_status); return u.l; } @@ -2870,7 +2870,7 @@ { CPU_FloatU u; - u.f = uint32_to_float32(val, &env->spe_status); + u.f = uint32_to_float32(val, &env->vec_status); return u.l; } @@ -2884,7 +2884,7 @@ if (unlikely(float32_is_nan(u.f))) return 0; - return float32_to_int32(u.f, &env->spe_status); + return float32_to_int32(u.f, &env->vec_status); } static always_inline uint32_t efsctui (uint32_t val) @@ -2896,7 +2896,7 @@ if (unlikely(float32_is_nan(u.f))) return 0; - return float32_to_uint32(u.f, &env->spe_status); + return float32_to_uint32(u.f, &env->vec_status); } static always_inline uint32_t efsctsiz (uint32_t val) @@ -2908,7 +2908,7 @@ if (unlikely(float32_is_nan(u.f))) return 0; - return float32_to_int32_round_to_zero(u.f, &env->spe_status); + return float32_to_int32_round_to_zero(u.f, &env->vec_status); } static always_inline uint32_t efsctuiz (uint32_t val) @@ -2920,7 +2920,7 @@ if (unlikely(float32_is_nan(u.f))) return 0; - return float32_to_uint32_round_to_zero(u.f, &env->spe_status); + return float32_to_uint32_round_to_zero(u.f, &env->vec_status); } static always_inline uint32_t efscfsf (uint32_t val) @@ -2928,9 +2928,9 @@ CPU_FloatU u; float32 tmp; - u.f = int32_to_float32(val, &env->spe_status); - tmp = int64_to_float32(1ULL << 32, &env->spe_status); - u.f = float32_div(u.f, tmp, &env->spe_status); + u.f = int32_to_float32(val, &env->vec_status); + tmp = int64_to_float32(1ULL << 32, &env->vec_status); + u.f = float32_div(u.f, tmp, &env->vec_status); return u.l; } @@ -2940,9 +2940,9 @@ CPU_FloatU u; float32 tmp; - u.f = uint32_to_float32(val, &env->spe_status); - tmp = uint64_to_float32(1ULL << 32, &env->spe_status); - u.f = float32_div(u.f, tmp, &env->spe_status); + u.f = uint32_to_float32(val, &env->vec_status); + tmp = uint64_to_float32(1ULL << 32, &env->vec_status); + u.f = float32_div(u.f, tmp, &env->vec_status); return u.l; } @@ -2956,10 +2956,10 @@ /* NaN are not treated the same way IEEE 754 does */ if (unlikely(float32_is_nan(u.f))) return 0; - tmp = uint64_to_float32(1ULL << 32, &env->spe_status); - u.f = float32_mul(u.f, tmp, &env->spe_status); + tmp = uint64_to_float32(1ULL << 32, &env->vec_status); + u.f = float32_mul(u.f, tmp, &env->vec_status); - return float32_to_int32(u.f, &env->spe_status); + return float32_to_int32(u.f, &env->vec_status); } static always_inline uint32_t efsctuf (uint32_t val) @@ -2971,10 +2971,10 @@ /* NaN are not treated the same way IEEE 754 does */ if (unlikely(float32_is_nan(u.f))) return 0; - tmp = uint64_to_float32(1ULL << 32, &env->spe_status); - u.f = float32_mul(u.f, tmp, &env->spe_status); + tmp = uint64_to_float32(1ULL << 32, &env->vec_status); + u.f = float32_mul(u.f, tmp, &env->vec_status); - return float32_to_uint32(u.f, &env->spe_status); + return float32_to_uint32(u.f, &env->vec_status); } #define HELPER_SPE_SINGLE_CONV(name) \ @@ -3036,7 +3036,7 @@ CPU_FloatU u1, u2; u1.l = op1; u2.l = op2; - u1.f = float32_add(u1.f, u2.f, &env->spe_status); + u1.f = float32_add(u1.f, u2.f, &env->vec_status); return u1.l; } @@ -3045,7 +3045,7 @@ CPU_FloatU u1, u2; u1.l = op1; u2.l = op2; - u1.f = float32_sub(u1.f, u2.f, &env->spe_status); + u1.f = float32_sub(u1.f, u2.f, &env->vec_status); return u1.l; } @@ -3054,7 +3054,7 @@ CPU_FloatU u1, u2; u1.l = op1; u2.l = op2; - u1.f = float32_mul(u1.f, u2.f, &env->spe_status); + u1.f = float32_mul(u1.f, u2.f, &env->vec_status); return u1.l; } @@ -3063,7 +3063,7 @@ CPU_FloatU u1, u2; u1.l = op1; u2.l = op2; - u1.f = float32_div(u1.f, u2.f, &env->spe_status); + u1.f = float32_div(u1.f, u2.f, &env->vec_status); return u1.l; } @@ -3102,7 +3102,7 @@ CPU_FloatU u1, u2; u1.l = op1; u2.l = op2; - return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0; + return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0; } static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2) @@ -3110,7 +3110,7 @@ CPU_FloatU u1, u2; u1.l = op1; u2.l = op2; - return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4; + return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4; } static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2) @@ -3118,7 +3118,7 @@ CPU_FloatU u1, u2; u1.l = op1; u2.l = op2; - return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0; + return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0; } static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2) @@ -3185,7 +3185,7 @@ { CPU_DoubleU u; - u.d = int32_to_float64(val, &env->spe_status); + u.d = int32_to_float64(val, &env->vec_status); return u.ll; } @@ -3194,7 +3194,7 @@ { CPU_DoubleU u; - u.d = int64_to_float64(val, &env->spe_status); + u.d = int64_to_float64(val, &env->vec_status); return u.ll; } @@ -3203,7 +3203,7 @@ { CPU_DoubleU u; - u.d = uint32_to_float64(val, &env->spe_status); + u.d = uint32_to_float64(val, &env->vec_status); return u.ll; } @@ -3212,7 +3212,7 @@ { CPU_DoubleU u; - u.d = uint64_to_float64(val, &env->spe_status); + u.d = uint64_to_float64(val, &env->vec_status); return u.ll; } @@ -3226,7 +3226,7 @@ if (unlikely(float64_is_nan(u.d))) return 0; - return float64_to_int32(u.d, &env->spe_status); + return float64_to_int32(u.d, &env->vec_status); } uint32_t helper_efdctui (uint64_t val) @@ -3238,7 +3238,7 @@ if (unlikely(float64_is_nan(u.d))) return 0; - return float64_to_uint32(u.d, &env->spe_status); + return float64_to_uint32(u.d, &env->vec_status); } uint32_t helper_efdctsiz (uint64_t val) @@ -3250,7 +3250,7 @@ if (unlikely(float64_is_nan(u.d))) return 0; - return float64_to_int32_round_to_zero(u.d, &env->spe_status); + return float64_to_int32_round_to_zero(u.d, &env->vec_status); } uint64_t helper_efdctsidz (uint64_t val) @@ -3262,7 +3262,7 @@ if (unlikely(float64_is_nan(u.d))) return 0; - return float64_to_int64_round_to_zero(u.d, &env->spe_status); + return float64_to_int64_round_to_zero(u.d, &env->vec_status); } uint32_t helper_efdctuiz (uint64_t val) @@ -3274,7 +3274,7 @@ if (unlikely(float64_is_nan(u.d))) return 0; - return float64_to_uint32_round_to_zero(u.d, &env->spe_status); + return float64_to_uint32_round_to_zero(u.d, &env->vec_status); } uint64_t helper_efdctuidz (uint64_t val) @@ -3286,7 +3286,7 @@ if (unlikely(float64_is_nan(u.d))) return 0; - return float64_to_uint64_round_to_zero(u.d, &env->spe_status); + return float64_to_uint64_round_to_zero(u.d, &env->vec_status); } uint64_t helper_efdcfsf (uint32_t val) @@ -3294,9 +3294,9 @@ CPU_DoubleU u; float64 tmp; - u.d = int32_to_float64(val, &env->spe_status); - tmp = int64_to_float64(1ULL << 32, &env->spe_status); - u.d = float64_div(u.d, tmp, &env->spe_status); + u.d = int32_to_float64(val, &env->vec_status); + tmp = int64_to_float64(1ULL << 32, &env->vec_status); + u.d = float64_div(u.d, tmp, &env->vec_status); return u.ll; } @@ -3306,9 +3306,9 @@ CPU_DoubleU u; float64 tmp; - u.d = uint32_to_float64(val, &env->spe_status); - tmp = int64_to_float64(1ULL << 32, &env->spe_status); - u.d = float64_div(u.d, tmp, &env->spe_status); + u.d = uint32_to_float64(val, &env->vec_status); + tmp = int64_to_float64(1ULL << 32, &env->vec_status); + u.d = float64_div(u.d, tmp, &env->vec_status); return u.ll; } @@ -3322,10 +3322,10 @@ /* NaN are not treated the same way IEEE 754 does */ if (unlikely(float64_is_nan(u.d))) return 0; - tmp = uint64_to_float64(1ULL << 32, &env->spe_status); - u.d = float64_mul(u.d, tmp, &env->spe_status); + tmp = uint64_to_float64(1ULL << 32, &env->vec_status); + u.d = float64_mul(u.d, tmp, &env->vec_status); - return float64_to_int32(u.d, &env->spe_status); + return float64_to_int32(u.d, &env->vec_status); } uint32_t helper_efdctuf (uint64_t val) @@ -3337,10 +3337,10 @@ /* NaN are not treated the same way IEEE 754 does */ if (unlikely(float64_is_nan(u.d))) return 0; - tmp = uint64_to_float64(1ULL << 32, &env->spe_status); - u.d = float64_mul(u.d, tmp, &env->spe_status); + tmp = uint64_to_float64(1ULL << 32, &env->vec_status); + u.d = float64_mul(u.d, tmp, &env->vec_status); - return float64_to_uint32(u.d, &env->spe_status); + return float64_to_uint32(u.d, &env->vec_status); } uint32_t helper_efscfd (uint64_t val) @@ -3349,7 +3349,7 @@ CPU_FloatU u2; u1.ll = val; - u2.f = float64_to_float32(u1.d, &env->spe_status); + u2.f = float64_to_float32(u1.d, &env->vec_status); return u2.l; } @@ -3360,7 +3360,7 @@ CPU_FloatU u1; u1.l = val; - u2.d = float32_to_float64(u1.f, &env->spe_status); + u2.d = float32_to_float64(u1.f, &env->vec_status); return u2.ll; } @@ -3371,7 +3371,7 @@ CPU_DoubleU u1, u2; u1.ll = op1; u2.ll = op2; - u1.d = float64_add(u1.d, u2.d, &env->spe_status); + u1.d = float64_add(u1.d, u2.d, &env->vec_status); return u1.ll; } @@ -3380,7 +3380,7 @@ CPU_DoubleU u1, u2; u1.ll = op1; u2.ll = op2; - u1.d = float64_sub(u1.d, u2.d, &env->spe_status); + u1.d = float64_sub(u1.d, u2.d, &env->vec_status); return u1.ll; } @@ -3389,7 +3389,7 @@ CPU_DoubleU u1, u2; u1.ll = op1; u2.ll = op2; - u1.d = float64_mul(u1.d, u2.d, &env->spe_status); + u1.d = float64_mul(u1.d, u2.d, &env->vec_status); return u1.ll; } @@ -3398,7 +3398,7 @@ CPU_DoubleU u1, u2; u1.ll = op1; u2.ll = op2; - u1.d = float64_div(u1.d, u2.d, &env->spe_status); + u1.d = float64_div(u1.d, u2.d, &env->vec_status); return u1.ll; } @@ -3408,7 +3408,7 @@ CPU_DoubleU u1, u2; u1.ll = op1; u2.ll = op2; - return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0; + return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0; } uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2) @@ -3416,7 +3416,7 @@ CPU_DoubleU u1, u2; u1.ll = op1; u2.ll = op2; - return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4; + return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4; } uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2) @@ -3424,7 +3424,7 @@ CPU_DoubleU u1, u2; u1.ll = op1; u2.ll = op2; - return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0; + return float64_eq(u1.d, u2.d, &env->vec_status) ? 4 : 0; } uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)