From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LZ5Vu-0008Bl-C5 for qemu-devel@nongnu.org; Mon, 16 Feb 2009 10:36:06 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LZ5Vt-0008BO-Se for qemu-devel@nongnu.org; Mon, 16 Feb 2009 10:36:05 -0500 Received: from [199.232.76.173] (port=45152 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LZ5Vt-0008BJ-I5 for qemu-devel@nongnu.org; Mon, 16 Feb 2009 10:36:05 -0500 Received: from savannah.gnu.org ([199.232.41.3]:42697 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LZ5Vt-0005Fp-6N for qemu-devel@nongnu.org; Mon, 16 Feb 2009 10:36:05 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1LZ5Vs-0006hy-D6 for qemu-devel@nongnu.org; Mon, 16 Feb 2009 15:36:04 +0000 Received: from aliguori by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1LZ5Vs-0006hu-3g for qemu-devel@nongnu.org; Mon, 16 Feb 2009 15:36:04 +0000 MIME-Version: 1.0 Errors-To: aliguori Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Anthony Liguori Message-Id: Date: Mon, 16 Feb 2009 15:36:04 +0000 Subject: [Qemu-devel] [6624] Fix GPE registers read/write handling. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 6624 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6624 Author: aliguori Date: 2009-02-16 15:36:03 +0000 (Mon, 16 Feb 2009) Log Message: ----------- Fix GPE registers read/write handling. (Gleb Natapov) For STS register bit are cleared by writing 1 into it. Signed-off-by: Gleb Natapov Signed-off-by: Anthony Liguori Modified Paths: -------------- trunk/hw/acpi.c Modified: trunk/hw/acpi.c =================================================================== --- trunk/hw/acpi.c 2009-02-16 15:34:18 UTC (rev 6623) +++ trunk/hw/acpi.c 2009-02-16 15:36:03 UTC (rev 6624) @@ -579,22 +579,25 @@ static struct gpe_regs gpe; static struct pci_status pci0_status; +static uint32_t gpe_read_val(uint16_t val, uint32_t addr) +{ + if (addr & 1) + return (val >> 8) & 0xff; + return val & 0xff; +} + static uint32_t gpe_readb(void *opaque, uint32_t addr) { uint32_t val = 0; struct gpe_regs *g = opaque; switch (addr) { case GPE_BASE: - val = g->sts & 0xFF; - break; case GPE_BASE + 1: - val = (g->sts >> 8) & 0xFF; + val = gpe_read_val(g->sts, addr); break; case GPE_BASE + 2: - val = g->en & 0xFF; - break; case GPE_BASE + 3: - val = (g->en >> 8) & 0xFF; + val = gpe_read_val(g->en, addr); break; default: break; @@ -606,21 +609,37 @@ return val; } +static void gpe_write_val(uint16_t *cur, int addr, uint32_t val) +{ + if (addr & 1) + *cur = (*cur & 0xff) | (val << 8); + else + *cur = (*cur & 0xff00) | (val & 0xff); +} + +static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val) +{ + uint16_t x1, x0 = val & 0xff; + int shift = (addr & 1) ? 8 : 0; + + x1 = (*cur >> shift) & 0xff; + + x1 = x1 & ~x0; + + *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift); +} + static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) { struct gpe_regs *g = opaque; switch (addr) { case GPE_BASE: - g->sts = (g->sts & ~0xFFFF) | (val & 0xFFFF); - break; case GPE_BASE + 1: - g->sts = (g->sts & 0xFFFF) | (val << 8); + gpe_reset_val(&g->sts, addr, val); break; case GPE_BASE + 2: - g->en = (g->en & ~0xFFFF) | (val & 0xFFFF); - break; case GPE_BASE + 3: - g->en = (g->en & 0xFFFF) | (val << 8); + gpe_write_val(&g->en, addr, val); break; default: break;