[Qemu-devel] [6667] Fix mtcrf/mfcr

[Qemu-devel] [6667] Fix mtcrf/mfcr

[malc]

Revision: 6667
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6667
Author:   malc
Date:     2009-03-02 22:39:39 +0000 (Mon, 02 Mar 2009)
Log Message:
-----------
Fix mtcrf/mfcr

Noticed by Alexander Graf

Modified Paths:
--------------
    trunk/target-ppc/translate.c

Modified: trunk/target-ppc/translate.c
===================================================================
--- trunk/target-ppc/translate.c	2009-03-02 17:13:21 UTC (rev 6666)
+++ trunk/target-ppc/translate.c	2009-03-02 22:39:39 UTC (rev 6667)
@@ -3843,9 +3843,11 @@
 
     if (likely(ctx->opcode & 0x00100000)) {
         crm = CRM(ctx->opcode);
-        if (likely((crm ^ (crm - 1)) == 0)) {
-            crn = ffs(crm);
+        if (likely(crm && ((crm & (crm - 1)) == 0))) {
+            crn = ffs (crm) - 1;
             tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
+            tcg_gen_shli_i32(cpu_gpr[rD(ctx->opcode)],
+                             cpu_gpr[rD(ctx->opcode)], crn * 4);
         }
     } else {
         gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
@@ -3935,13 +3937,15 @@
     uint32_t crm, crn;
 
     crm = CRM(ctx->opcode);
-    if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
-        TCGv_i32 temp = tcg_temp_new_i32();
-        crn = ffs(crm);
-        tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
-        tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
-        tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
-        tcg_temp_free_i32(temp);
+    if (likely((ctx->opcode & 0x00100000))) {
+        if (crm && ((crm & (crm - 1)) == 0)) {
+            TCGv_i32 temp = tcg_temp_new_i32();
+            crn = ffs (crm) - 1;
+            tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
+            tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
+            tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
+            tcg_temp_free_i32(temp);
+        }
     } else {
         TCGv_i32 temp = tcg_const_i32(crm);
         gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);

Re: [Qemu-devel] [6667] Fix mtcrf/mfcr

[Stuart Brady]

On Mon, Mar 02, 2009 at 10:39:40PM +0000, malc wrote:
> Modified: trunk/target-ppc/translate.c
> ===================================================================
> --- trunk/target-ppc/translate.c	2009-03-02 17:13:21 UTC (rev 6666)
> +++ trunk/target-ppc/translate.c	2009-03-02 22:39:39 UTC (rev 6667)
> @@ -3843,9 +3843,11 @@
...
>              tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);                                      
> +            tcg_gen_shli_i32(cpu_gpr[rD(ctx->opcode)],
> +                             cpu_gpr[rD(ctx->opcode)], crn * 4);

This breaks compilation of PPC64 targets with DEBUG_TCGV enabled.

Regards,
-- 
Stuart Brady

Re: [Qemu-devel] [6667] Fix mtcrf/mfcr

[Aurelien Jarno]

On Sat, Mar 07, 2009 at 08:08:59PM +0000, Stuart Brady wrote:
> On Mon, Mar 02, 2009 at 10:39:40PM +0000, malc wrote:
> > Modified: trunk/target-ppc/translate.c
> > ===================================================================
> > --- trunk/target-ppc/translate.c	2009-03-02 17:13:21 UTC (rev 6666)
> > +++ trunk/target-ppc/translate.c	2009-03-02 22:39:39 UTC (rev 6667)
> > @@ -3843,9 +3843,11 @@
> ...
> >              tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);                                      
> > +            tcg_gen_shli_i32(cpu_gpr[rD(ctx->opcode)],
> > +                             cpu_gpr[rD(ctx->opcode)], crn * 4);
> 
> This breaks compilation of PPC64 targets with DEBUG_TCGV enabled.
> 

That should be fixed in SVN, thanks.

-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net