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From: Blue Swirl <blauwirbel@gmail.com>
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Date: Sat, 07 Mar 2009 20:55:31 +0000
Subject: [Qemu-devel] [6753] Implement mtfsf.L encoding
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Revision: 6753
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6753
Author:   blueswir1
Date:     2009-03-07 20:55:31 +0000 (Sat, 07 Mar 2009)
Log Message:
-----------
Implement mtfsf.L encoding

Mtfsf can have the L bit set, so all the register contents get stored
in FPSCR. Linux uses it, so let's implement it.

Signed-off-by: Alexander Graf <alex@csgraf.de>

Modified Paths:
--------------
    trunk/target-ppc/translate.c

Modified: trunk/target-ppc/translate.c
===================================================================
--- trunk/target-ppc/translate.c	2009-03-07 20:54:59 UTC (rev 6752)
+++ trunk/target-ppc/translate.c	2009-03-07 20:55:31 UTC (rev 6753)
@@ -2420,9 +2420,10 @@
 }
 
 /* mtfsf */
-GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
+GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT)
 {
     TCGv_i32 t0;
+    int L = ctx->opcode & 0x02000000;
 
     if (unlikely(!ctx->fpu_enabled)) {
         gen_exception(ctx, POWERPC_EXCP_FPU);
@@ -2431,7 +2432,10 @@
     /* NIP cannot be restored if the memory exception comes from an helper */
     gen_update_nip(ctx, ctx->nip - 4);
     gen_reset_fpstatus();
-    t0 = tcg_const_i32(FM(ctx->opcode));
+    if (L)
+        t0 = tcg_const_i32(0xff);
+    else
+        t0 = tcg_const_i32(FM(ctx->opcode));
     gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
     tcg_temp_free_i32(t0);
     if (unlikely(Rc(ctx->opcode) != 0)) {