From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Lg4Zg-0004vv-NY for qemu-devel@nongnu.org; Sat, 07 Mar 2009 17:00:52 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Lg4Zf-0004vN-Vi for qemu-devel@nongnu.org; Sat, 07 Mar 2009 17:00:52 -0500 Received: from [199.232.76.173] (port=58146 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Lg4Zf-0004vG-Od for qemu-devel@nongnu.org; Sat, 07 Mar 2009 17:00:51 -0500 Received: from savannah.gnu.org ([199.232.41.3]:43260 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Lg4Zf-00087l-AM for qemu-devel@nongnu.org; Sat, 07 Mar 2009 17:00:51 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1Lg4Ze-00081i-Dt for qemu-devel@nongnu.org; Sat, 07 Mar 2009 22:00:50 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.69) (envelope-from ) id 1Lg4Zd-00081c-My for qemu-devel@nongnu.org; Sat, 07 Mar 2009 22:00:50 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Sat, 07 Mar 2009 22:00:49 +0000 Subject: [Qemu-devel] [6769] Fix off-by-one errors for Altivec and SPE registers Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 6769 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6769 Author: aurel32 Date: 2009-03-07 22:00:49 +0000 (Sat, 07 Mar 2009) Log Message: ----------- Fix off-by-one errors for Altivec and SPE registers Altivec and SPE both have 34 registers in their register sets, not 35 with a missing register 32. GDB would ask for register 32 of the Altivec (resp. SPE) registers and the code would claim it had zero width. The QEMU GDB stub code would then return an E14 to GDB, which would complain about not being sure whether p packets were supported or not. Signed-off-by: Nathan Froyd Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/target-ppc/translate_init.c Modified: trunk/target-ppc/translate_init.c =================================================================== --- trunk/target-ppc/translate_init.c 2009-03-07 22:00:29 UTC (rev 6768) +++ trunk/target-ppc/translate_init.c 2009-03-07 22:00:49 UTC (rev 6769) @@ -9379,11 +9379,11 @@ #endif return 16; } - if (n == 33) { + if (n == 32) { stl_p(mem_buf, env->vscr); return 4; } - if (n == 34) { + if (n == 33) { stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]); return 4; } @@ -9402,11 +9402,11 @@ #endif return 16; } - if (n == 33) { + if (n == 32) { env->vscr = ldl_p(mem_buf); return 4; } - if (n == 34) { + if (n == 33) { env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf); return 4; } @@ -9423,11 +9423,11 @@ #endif return 4; } - if (n == 33) { + if (n == 32) { stq_p(mem_buf, env->spe_acc); return 8; } - if (n == 34) { + if (n == 33) { /* SPEFSCR not implemented */ memset(mem_buf, 0, 4); return 4; @@ -9447,11 +9447,11 @@ #endif return 4; } - if (n == 33) { + if (n == 32) { env->spe_acc = ldq_p(mem_buf); return 8; } - if (n == 34) { + if (n == 33) { /* SPEFSCR not implemented */ return 4; }