From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Lg4Zn-0004zT-Sj for qemu-devel@nongnu.org; Sat, 07 Mar 2009 17:00:59 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Lg4Zn-0004z3-9h for qemu-devel@nongnu.org; Sat, 07 Mar 2009 17:00:59 -0500 Received: from [199.232.76.173] (port=58147 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Lg4Zm-0004yv-Ud for qemu-devel@nongnu.org; Sat, 07 Mar 2009 17:00:59 -0500 Received: from savannah.gnu.org ([199.232.41.3]:43263 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Lg4Zm-00088B-FR for qemu-devel@nongnu.org; Sat, 07 Mar 2009 17:00:58 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1Lg4Zl-00082Y-Ml for qemu-devel@nongnu.org; Sat, 07 Mar 2009 22:00:57 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.69) (envelope-from ) id 1Lg4Zl-00082U-DZ for qemu-devel@nongnu.org; Sat, 07 Mar 2009 22:00:57 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Sat, 07 Mar 2009 22:00:57 +0000 Subject: [Qemu-devel] [6770] Work around QEMU GDB stub suboptimality Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 6770 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6770 Author: aurel32 Date: 2009-03-07 22:00:56 +0000 (Sat, 07 Mar 2009) Log Message: ----------- Work around QEMU GDB stub suboptimality The current XML files claim, on floating point-supporting Power chips, that $f0 is register 70. This would be fine, except that register 70 for non-XML-aware GDB is FPSCR. More importantly, 70 is less than NUM_CORE_REGS (71) for Power, so a request for register 70 goes to the "core" register reading routines, rather than the floating-point register read routine we registered with gdb_register_coprocessor. Therefore, when we are talking to an XML-aware GDB, we claim that register has zero width, which causes the rest of QEMU's GDB stub to send an error back to GDB, which causes GDB to be unable to read the floating-point registers. (The problem is also present for SPE registers and occurs in a slightly different way for Altivec registers.) The best way to fix this is to have the "core register" XML files for PPC32 and PPC64 claim that there is a 4-byte register 70, which causes $f0 to be register 71, and everything works just fine from that point forward. Signed-off-by: Nathan Froyd Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/gdb-xml/power-core.xml trunk/gdb-xml/power64-core.xml Modified: trunk/gdb-xml/power-core.xml =================================================================== --- trunk/gdb-xml/power-core.xml 2009-03-07 22:00:49 UTC (rev 6769) +++ trunk/gdb-xml/power-core.xml 2009-03-07 22:00:56 UTC (rev 6770) @@ -46,4 +46,13 @@ + + Modified: trunk/gdb-xml/power64-core.xml =================================================================== --- trunk/gdb-xml/power64-core.xml 2009-03-07 22:00:49 UTC (rev 6769) +++ trunk/gdb-xml/power64-core.xml 2009-03-07 22:00:56 UTC (rev 6770) @@ -46,4 +46,13 @@ + +