From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LncLG-00034L-Ma for qemu-devel@nongnu.org; Sat, 28 Mar 2009 13:29:10 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LncLF-00033M-8U for qemu-devel@nongnu.org; Sat, 28 Mar 2009 13:29:09 -0400 Received: from [199.232.76.173] (port=57018 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LncLE-00032x-Kh for qemu-devel@nongnu.org; Sat, 28 Mar 2009 13:29:08 -0400 Received: from savannah.gnu.org ([199.232.41.3]:54371 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LncLE-0006Bf-DO for qemu-devel@nongnu.org; Sat, 28 Mar 2009 13:29:08 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1LncLD-0005hm-Q2 for qemu-devel@nongnu.org; Sat, 28 Mar 2009 17:29:07 +0000 Received: from aliguori by cvs.savannah.gnu.org with local (Exim 4.69) (envelope-from ) id 1LncLD-0005hf-It for qemu-devel@nongnu.org; Sat, 28 Mar 2009 17:29:07 +0000 MIME-Version: 1.0 Errors-To: aliguori Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Anthony Liguori Message-Id: Date: Sat, 28 Mar 2009 17:29:07 +0000 Subject: [Qemu-devel] [6901] Clean some PCI defines (Stefan Weil) Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 6901 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6901 Author: aliguori Date: 2009-03-28 17:29:07 +0000 (Sat, 28 Mar 2009) Log Message: ----------- Clean some PCI defines (Stefan Weil) this patch adds some more defines from linux/pci_regs.h to hw/pci.h. There is now no longer a need to define them in eepro100.c, so they were removed there. Some defines from linux/pci_regs.h had similar, but not the same defines in hw/pci.h (PCI_REVISION_ID / PCI_REVISION, PCI_SUBSYSTEM_VENDOR_ID / PCI_SUBVENDOR_ID, PCI_SUBSYSTEM_ID / PCI_SUBDEVICE_ID). I suggest to use the "standard" from linux/pci_regs.h and replace the "old" Qemu ones. To facilitate the migration, my patch does not remove the old defines but marks them as obsolete. After a migration to the "standard" defines, pci.h could use linux/pci_regs.h which is far more complete. The patch is needed for an updated maintainer version of hw/eepro100.c which I'd like to see in Qemu stable. * Remove declarations already declared in header file from eepro100.c * Add missing declarations from pci_regs.h to pci.h * Mark "non-standard" declarations in pci.h as obsolete Signed-off-by: Stefan Weil Signed-off-by: Anthony Liguori Modified Paths: -------------- trunk/hw/eepro100.c trunk/hw/pci.h Modified: trunk/hw/eepro100.c =================================================================== --- trunk/hw/eepro100.c 2009-03-28 17:29:02 UTC (rev 6900) +++ trunk/hw/eepro100.c 2009-03-28 17:29:07 UTC (rev 6901) @@ -47,12 +47,6 @@ /* Common declarations for all PCI devices. */ -#define PCI_DEVICE_ID 0x02 /* 16 bits */ -#define PCI_COMMAND 0x04 /* 16 bits */ -#define PCI_STATUS 0x06 /* 16 bits */ - -#define PCI_REVISION_ID 0x08 /* 8 bits */ - #define PCI_CONFIG_8(offset, value) \ (pci_conf[offset] = (value)) #define PCI_CONFIG_16(offset, value) \ Modified: trunk/hw/pci.h =================================================================== --- trunk/hw/pci.h 2009-03-28 17:29:02 UTC (rev 6900) +++ trunk/hw/pci.h 2009-03-28 17:29:07 UTC (rev 6901) @@ -55,7 +55,7 @@ #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 -#define PCI_VENDOR_ID_INTEL 0x8086 +/* Intel (0x8086) */ #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ @@ -92,20 +92,27 @@ #define PCI_DEVICES_MAX 64 +/* Declarations from linux/pci_regs.h */ #define PCI_VENDOR_ID 0x00 /* 16 bits */ #define PCI_DEVICE_ID 0x02 /* 16 bits */ #define PCI_COMMAND 0x04 /* 16 bits */ #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ -#define PCI_REVISION 0x08 +#define PCI_STATUS 0x06 /* 16 bits */ +#define PCI_REVISION_ID 0x08 /* 8 bits */ #define PCI_CLASS_DEVICE 0x0a /* Device class */ -#define PCI_SUBVENDOR_ID 0x2c /* 16 bits */ -#define PCI_SUBDEVICE_ID 0x2e /* 16 bits */ +#define PCI_HEADER_TYPE 0x0e /* 8 bits */ +#define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */ +#define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */ #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ #define PCI_MIN_GNT 0x3e /* 8 bits */ #define PCI_MAX_LAT 0x3f /* 8 bits */ +#define PCI_REVISION 0x08 /* obsolete, use PCI_REVISION_ID */ +#define PCI_SUBVENDOR_ID 0x2c /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */ +#define PCI_SUBDEVICE_ID 0x2e /* obsolete, use PCI_SUBSYSTEM_ID */ + /* Bits in the PCI Status Register (PCI 2.3 spec) */ #define PCI_STATUS_RESERVED1 0x007 #define PCI_STATUS_INT_STATUS 0x008