[Qemu-devel] [6924] target-alpha: fix bug: integer conditional branch offset is 21 bits wide.

[Qemu-devel] [6924] target-alpha: fix bug: integer conditional branch offset is 21 bits wide.

[Aurelien Jarno]

Revision: 6924
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6924
Author:   aurel32
Date:     2009-03-29 00:13:56 +0000 (Sun, 29 Mar 2009)
Log Message:
-----------
target-alpha: fix bug: integer conditional branch offset is 21 bits wide.

Signed-off-by: Tristan Gingold <gingold@adacore.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

Modified Paths:
--------------
    trunk/target-alpha/translate.c

Modified: trunk/target-alpha/translate.c
===================================================================
--- trunk/target-alpha/translate.c	2009-03-29 00:13:47 UTC (rev 6923)
+++ trunk/target-alpha/translate.c	2009-03-29 00:13:56 UTC (rev 6924)
@@ -290,7 +290,7 @@
 
 static always_inline void gen_bcond (DisasContext *ctx,
                                      TCGCond cond,
-                                     int ra, int32_t disp16, int mask)
+                                     int ra, int32_t disp, int mask)
 {
     int l1, l2;
 
@@ -313,7 +313,7 @@
     tcg_gen_movi_i64(cpu_pc, ctx->pc);
     tcg_gen_br(l2);
     gen_set_label(l1);
-    tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2));
+    tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp << 2));
     gen_set_label(l2);
 }
 
@@ -2285,42 +2285,42 @@
         break;
     case 0x38:
         /* BLBC */
-        gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 1);
+        gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 1);
         ret = 1;
         break;
     case 0x39:
         /* BEQ */
-        gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 0);
+        gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 0);
         ret = 1;
         break;
     case 0x3A:
         /* BLT */
-        gen_bcond(ctx, TCG_COND_LT, ra, disp16, 0);
+        gen_bcond(ctx, TCG_COND_LT, ra, disp21, 0);
         ret = 1;
         break;
     case 0x3B:
         /* BLE */
-        gen_bcond(ctx, TCG_COND_LE, ra, disp16, 0);
+        gen_bcond(ctx, TCG_COND_LE, ra, disp21, 0);
         ret = 1;
         break;
     case 0x3C:
         /* BLBS */
-        gen_bcond(ctx, TCG_COND_NE, ra, disp16, 1);
+        gen_bcond(ctx, TCG_COND_NE, ra, disp21, 1);
         ret = 1;
         break;
     case 0x3D:
         /* BNE */
-        gen_bcond(ctx, TCG_COND_NE, ra, disp16, 0);
+        gen_bcond(ctx, TCG_COND_NE, ra, disp21, 0);
         ret = 1;
         break;
     case 0x3E:
         /* BGE */
-        gen_bcond(ctx, TCG_COND_GE, ra, disp16, 0);
+        gen_bcond(ctx, TCG_COND_GE, ra, disp21, 0);
         ret = 1;
         break;
     case 0x3F:
         /* BGT */
-        gen_bcond(ctx, TCG_COND_GT, ra, disp16, 0);
+        gen_bcond(ctx, TCG_COND_GT, ra, disp21, 0);
         ret = 1;
         break;
     invalid_opc: