From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [6932] target-mips: optimize gen_cl()
Date: Sun, 29 Mar 2009 01:18:16 +0000 [thread overview]
Message-ID: <E1LnjfE-00082F-Ii@cvs.savannah.gnu.org> (raw)
Revision: 6932
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6932
Author: aurel32
Date: 2009-03-29 01:18:16 +0000 (Sun, 29 Mar 2009)
Log Message:
-----------
target-mips: optimize gen_cl()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Modified Paths:
--------------
trunk/target-mips/translate.c
Modified: trunk/target-mips/translate.c
===================================================================
--- trunk/target-mips/translate.c 2009-03-29 01:18:03 UTC (rev 6931)
+++ trunk/target-mips/translate.c 2009-03-29 01:18:16 UTC (rev 6932)
@@ -2128,42 +2128,36 @@
int rd, int rs)
{
const char *opn = "CLx";
- TCGv t0 = tcg_temp_local_new();
+ TCGv t0;
if (rd == 0) {
/* Treat as NOP. */
MIPS_DEBUG("NOP");
- goto out;
+ return;
}
+ t0 = tcg_temp_new();
gen_load_gpr(t0, rs);
switch (opc) {
case OPC_CLO:
- gen_helper_clo(t0, t0);
+ gen_helper_clo(cpu_gpr[rd], t0);
opn = "clo";
break;
case OPC_CLZ:
- gen_helper_clz(t0, t0);
+ gen_helper_clz(cpu_gpr[rd], t0);
opn = "clz";
break;
#if defined(TARGET_MIPS64)
case OPC_DCLO:
- gen_helper_dclo(t0, t0);
+ gen_helper_dclo(cpu_gpr[rd], t0);
opn = "dclo";
break;
case OPC_DCLZ:
- gen_helper_dclz(t0, t0);
+ gen_helper_dclz(cpu_gpr[rd], t0);
opn = "dclz";
break;
#endif
- default:
- MIPS_INVAL(opn);
- generate_exception(ctx, EXCP_RI);
- goto out;
}
- gen_store_gpr(t0, rd);
MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
-
- out:
tcg_temp_free(t0);
}
@@ -7711,7 +7705,8 @@
case OPC_MUL:
gen_arith(env, ctx, op1, rd, rs, rt);
break;
- case OPC_CLZ ... OPC_CLO:
+ case OPC_CLO:
+ case OPC_CLZ:
check_insn(env, ctx, ISA_MIPS32);
gen_cl(ctx, op1, rd, rs);
break;
@@ -7728,7 +7723,8 @@
/* Treat as NOP. */
break;
#if defined(TARGET_MIPS64)
- case OPC_DCLZ ... OPC_DCLO:
+ case OPC_DCLO:
+ case OPC_DCLZ:
check_insn(env, ctx, ISA_MIPS64);
check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs);
reply other threads:[~2009-03-29 1:18 UTC|newest]
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