From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LnjfG-0003fI-Np for qemu-devel@nongnu.org; Sat, 28 Mar 2009 21:18:18 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LnjfF-0003eh-Un for qemu-devel@nongnu.org; Sat, 28 Mar 2009 21:18:18 -0400 Received: from [199.232.76.173] (port=37018 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LnjfF-0003eV-R1 for qemu-devel@nongnu.org; Sat, 28 Mar 2009 21:18:17 -0400 Received: from savannah.gnu.org ([199.232.41.3]:40382 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LnjfF-0003BE-KB for qemu-devel@nongnu.org; Sat, 28 Mar 2009 21:18:17 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1LnjfE-00082J-VL for qemu-devel@nongnu.org; Sun, 29 Mar 2009 01:18:17 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.69) (envelope-from ) id 1LnjfE-00082F-Ii for qemu-devel@nongnu.org; Sun, 29 Mar 2009 01:18:16 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Sun, 29 Mar 2009 01:18:16 +0000 Subject: [Qemu-devel] [6932] target-mips: optimize gen_cl() Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 6932 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6932 Author: aurel32 Date: 2009-03-29 01:18:16 +0000 (Sun, 29 Mar 2009) Log Message: ----------- target-mips: optimize gen_cl() Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/target-mips/translate.c Modified: trunk/target-mips/translate.c =================================================================== --- trunk/target-mips/translate.c 2009-03-29 01:18:03 UTC (rev 6931) +++ trunk/target-mips/translate.c 2009-03-29 01:18:16 UTC (rev 6932) @@ -2128,42 +2128,36 @@ int rd, int rs) { const char *opn = "CLx"; - TCGv t0 = tcg_temp_local_new(); + TCGv t0; if (rd == 0) { /* Treat as NOP. */ MIPS_DEBUG("NOP"); - goto out; + return; } + t0 = tcg_temp_new(); gen_load_gpr(t0, rs); switch (opc) { case OPC_CLO: - gen_helper_clo(t0, t0); + gen_helper_clo(cpu_gpr[rd], t0); opn = "clo"; break; case OPC_CLZ: - gen_helper_clz(t0, t0); + gen_helper_clz(cpu_gpr[rd], t0); opn = "clz"; break; #if defined(TARGET_MIPS64) case OPC_DCLO: - gen_helper_dclo(t0, t0); + gen_helper_dclo(cpu_gpr[rd], t0); opn = "dclo"; break; case OPC_DCLZ: - gen_helper_dclz(t0, t0); + gen_helper_dclz(cpu_gpr[rd], t0); opn = "dclz"; break; #endif - default: - MIPS_INVAL(opn); - generate_exception(ctx, EXCP_RI); - goto out; } - gen_store_gpr(t0, rd); MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]); - - out: tcg_temp_free(t0); } @@ -7711,7 +7705,8 @@ case OPC_MUL: gen_arith(env, ctx, op1, rd, rs, rt); break; - case OPC_CLZ ... OPC_CLO: + case OPC_CLO: + case OPC_CLZ: check_insn(env, ctx, ISA_MIPS32); gen_cl(ctx, op1, rd, rs); break; @@ -7728,7 +7723,8 @@ /* Treat as NOP. */ break; #if defined(TARGET_MIPS64) - case OPC_DCLZ ... OPC_DCLO: + case OPC_DCLO: + case OPC_DCLZ: check_insn(env, ctx, ISA_MIPS64); check_mips_64(ctx); gen_cl(ctx, op1, rd, rs);