From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LnxBd-0002wg-Vk for qemu-devel@nongnu.org; Sun, 29 Mar 2009 11:44:38 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LnxBc-0002wK-BS for qemu-devel@nongnu.org; Sun, 29 Mar 2009 11:44:37 -0400 Received: from [199.232.76.173] (port=34586 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LnxBc-0002wF-4F for qemu-devel@nongnu.org; Sun, 29 Mar 2009 11:44:36 -0400 Received: from savannah.gnu.org ([199.232.41.3]:59296 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LnxBb-0003GG-Od for qemu-devel@nongnu.org; Sun, 29 Mar 2009 11:44:35 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1LnxBb-0006dj-58 for qemu-devel@nongnu.org; Sun, 29 Mar 2009 15:44:35 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.69) (envelope-from ) id 1LnxBa-0006dT-Np for qemu-devel@nongnu.org; Sun, 29 Mar 2009 15:44:35 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Sun, 29 Mar 2009 15:44:34 +0000 Subject: [Qemu-devel] [6955] target-mips: optimize gen_compute_branch1() Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 6955 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6955 Author: aurel32 Date: 2009-03-29 15:44:34 +0000 (Sun, 29 Mar 2009) Log Message: ----------- target-mips: optimize gen_compute_branch1() Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/target-mips/translate.c Modified: trunk/target-mips/translate.c =================================================================== --- trunk/target-mips/translate.c 2009-03-29 15:40:59 UTC (rev 6954) +++ trunk/target-mips/translate.c 2009-03-29 15:44:34 UTC (rev 6955) @@ -643,18 +643,12 @@ } } -static inline void get_fp_cond (TCGv_i32 t) +static inline int get_fp_bit (int cc) { - TCGv_i32 r_tmp1 = tcg_temp_new_i32(); - TCGv_i32 r_tmp2 = tcg_temp_new_i32(); - - tcg_gen_shri_i32(r_tmp2, fpu_fcr31, 24); - tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xfe); - tcg_gen_shri_i32(r_tmp1, fpu_fcr31, 23); - tcg_gen_andi_i32(r_tmp1, r_tmp1, 0x1); - tcg_gen_or_i32(t, r_tmp1, r_tmp2); - tcg_temp_free_i32(r_tmp1); - tcg_temp_free_i32(r_tmp2); + if (cc) + return 24 + cc; + else + return 23; } #define FOP_CONDS(type, fmt, bits) \ @@ -5500,132 +5494,88 @@ switch (op) { case OPC_BC1F: - { - int l1 = gen_new_label(); - int l2 = gen_new_label(); - - get_fp_cond(t0); - tcg_gen_andi_i32(t0, t0, 0x1 << cc); - tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); - tcg_gen_movi_tl(bcond, 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_movi_tl(bcond, 1); - gen_set_label(l2); - } + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_not_i32(t0, t0); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); opn = "bc1f"; goto not_likely; case OPC_BC1FL: - { - int l1 = gen_new_label(); - int l2 = gen_new_label(); - - get_fp_cond(t0); - tcg_gen_andi_i32(t0, t0, 0x1 << cc); - tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); - tcg_gen_movi_tl(bcond, 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_movi_tl(bcond, 1); - gen_set_label(l2); - } + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_not_i32(t0, t0); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); opn = "bc1fl"; goto likely; case OPC_BC1T: - { - int l1 = gen_new_label(); - int l2 = gen_new_label(); - - get_fp_cond(t0); - tcg_gen_andi_i32(t0, t0, 0x1 << cc); - tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1); - tcg_gen_movi_tl(bcond, 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_movi_tl(bcond, 1); - gen_set_label(l2); - } + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); opn = "bc1t"; goto not_likely; case OPC_BC1TL: - { - int l1 = gen_new_label(); - int l2 = gen_new_label(); - - get_fp_cond(t0); - tcg_gen_andi_i32(t0, t0, 0x1 << cc); - tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1); - tcg_gen_movi_tl(bcond, 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_movi_tl(bcond, 1); - gen_set_label(l2); - } + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); opn = "bc1tl"; likely: ctx->hflags |= MIPS_HFLAG_BL; break; case OPC_BC1FANY2: { - int l1 = gen_new_label(); - int l2 = gen_new_label(); - - get_fp_cond(t0); - tcg_gen_andi_i32(t0, t0, 0x3 << cc); - tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); - tcg_gen_movi_tl(bcond, 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_movi_tl(bcond, 1); - gen_set_label(l2); + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); + tcg_gen_or_i32(t0, t0, t1); + tcg_temp_free_i32(t1); + tcg_gen_not_i32(t0, t0); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); } opn = "bc1any2f"; goto not_likely; case OPC_BC1TANY2: { - int l1 = gen_new_label(); - int l2 = gen_new_label(); - - get_fp_cond(t0); - tcg_gen_andi_i32(t0, t0, 0x3 << cc); - tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1); - tcg_gen_movi_tl(bcond, 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_movi_tl(bcond, 1); - gen_set_label(l2); + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); + tcg_gen_or_i32(t0, t0, t1); + tcg_temp_free_i32(t1); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); } opn = "bc1any2t"; goto not_likely; case OPC_BC1FANY4: { - int l1 = gen_new_label(); - int l2 = gen_new_label(); - - get_fp_cond(t0); - tcg_gen_andi_i32(t0, t0, 0xf << cc); - tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); - tcg_gen_movi_tl(bcond, 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_movi_tl(bcond, 1); - gen_set_label(l2); + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); + tcg_gen_or_i32(t0, t0, t1); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2)); + tcg_gen_or_i32(t0, t0, t1); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3)); + tcg_gen_or_i32(t0, t0, t1); + tcg_temp_free_i32(t1); + tcg_gen_not_i32(t0, t0); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); } opn = "bc1any4f"; goto not_likely; case OPC_BC1TANY4: { - int l1 = gen_new_label(); - int l2 = gen_new_label(); - - get_fp_cond(t0); - tcg_gen_andi_i32(t0, t0, 0xf << cc); - tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1); - tcg_gen_movi_tl(bcond, 0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_movi_tl(bcond, 1); - gen_set_label(l2); + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); + tcg_gen_or_i32(t0, t0, t1); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2)); + tcg_gen_or_i32(t0, t0, t1); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3)); + tcg_gen_or_i32(t0, t0, t1); + tcg_temp_free_i32(t1); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); } opn = "bc1any4t"; not_likely: