From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LnxC7-00033a-2b for qemu-devel@nongnu.org; Sun, 29 Mar 2009 11:45:07 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LnxC6-00033M-EJ for qemu-devel@nongnu.org; Sun, 29 Mar 2009 11:45:06 -0400 Received: from [199.232.76.173] (port=60569 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LnxC6-00033J-3f for qemu-devel@nongnu.org; Sun, 29 Mar 2009 11:45:06 -0400 Received: from savannah.gnu.org ([199.232.41.3]:59324 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LnxC5-0003Hg-Ma for qemu-devel@nongnu.org; Sun, 29 Mar 2009 11:45:05 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1LnxC4-0006nB-4S for qemu-devel@nongnu.org; Sun, 29 Mar 2009 15:45:04 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.69) (envelope-from ) id 1LnxC3-0006mb-Az for qemu-devel@nongnu.org; Sun, 29 Mar 2009 15:45:03 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Sun, 29 Mar 2009 15:45:03 +0000 Subject: [Qemu-devel] [6957] target-mips: optimize gen_movcf_*() Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 6957 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6957 Author: aurel32 Date: 2009-03-29 15:45:02 +0000 (Sun, 29 Mar 2009) Log Message: ----------- target-mips: optimize gen_movcf_*() Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/target-mips/translate.c Modified: trunk/target-mips/translate.c =================================================================== --- trunk/target-mips/translate.c 2009-03-29 15:44:50 UTC (rev 6956) +++ trunk/target-mips/translate.c 2009-03-29 15:45:02 UTC (rev 6957) @@ -5722,98 +5722,70 @@ static inline void gen_movcf_s (int fs, int fd, int cc, int tf) { - uint32_t ccbit; int cond; - TCGv_i32 r_tmp1 = tcg_temp_new_i32(); - TCGv_i32 fp0 = tcg_temp_local_new_i32(); + TCGv_i32 t0 = tcg_temp_new_i32(); int l1 = gen_new_label(); - if (cc) - ccbit = 1 << (24 + cc); - else - ccbit = 1 << 23; - if (tf) cond = TCG_COND_EQ; else cond = TCG_COND_NE; - gen_load_fpr32(fp0, fd); - tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit); - tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1); - tcg_temp_free_i32(r_tmp1); - gen_load_fpr32(fp0, fs); + tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_brcondi_i32(cond, t0, 0, l1); + gen_load_fpr32(t0, fs); + gen_store_fpr32(t0, fd); gen_set_label(l1); - gen_store_fpr32(fp0, fd); - tcg_temp_free_i32(fp0); + tcg_temp_free_i32(t0); } static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf) { - uint32_t ccbit; int cond; - TCGv_i32 r_tmp1 = tcg_temp_new_i32(); - TCGv_i64 fp0 = tcg_temp_local_new_i64(); + TCGv_i32 t0 = tcg_temp_new_i32(); + TCGv_i64 fp0; int l1 = gen_new_label(); - if (cc) - ccbit = 1 << (24 + cc); - else - ccbit = 1 << 23; - if (tf) cond = TCG_COND_EQ; else cond = TCG_COND_NE; - gen_load_fpr64(ctx, fp0, fd); - tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit); - tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1); - tcg_temp_free_i32(r_tmp1); + tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_brcondi_i32(cond, t0, 0, l1); + fp0 = tcg_temp_local_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_set_label(l1); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); + gen_set_label(l1); + tcg_temp_free_i32(t0); } static inline void gen_movcf_ps (int fs, int fd, int cc, int tf) { - uint32_t ccbit1, ccbit2; int cond; - TCGv_i32 r_tmp1 = tcg_temp_new_i32(); - TCGv_i32 fp0 = tcg_temp_local_new_i32(); + TCGv_i32 t0 = tcg_temp_new_i32(); int l1 = gen_new_label(); int l2 = gen_new_label(); - if (cc) { - ccbit1 = 1 << (24 + cc); - ccbit2 = 1 << (25 + cc); - } else { - ccbit1 = 1 << 23; - ccbit2 = 1 << 25; - } - if (tf) cond = TCG_COND_EQ; else cond = TCG_COND_NE; - gen_load_fpr32(fp0, fd); - tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit1); - tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1); - gen_load_fpr32(fp0, fs); + tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_brcondi_i32(cond, t0, 0, l1); + gen_load_fpr32(t0, fs); + gen_store_fpr32(t0, fd); gen_set_label(l1); - gen_store_fpr32(fp0, fd); - gen_load_fpr32h(fp0, fd); - tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit2); - tcg_gen_brcondi_i32(cond, r_tmp1, 0, l2); - gen_load_fpr32h(fp0, fs); + tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc+1)); + tcg_gen_brcondi_i32(cond, t0, 0, l2); + gen_load_fpr32h(t0, fs); + gen_store_fpr32h(t0, fd); gen_set_label(l2); - gen_store_fpr32h(fp0, fd); - tcg_temp_free_i32(r_tmp1); - tcg_temp_free_i32(fp0); + tcg_temp_free_i32(t0); }