From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LrJmp-0004GA-0Y for qemu-devel@nongnu.org; Tue, 07 Apr 2009 18:28:55 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LrJmn-0004Fy-Hm for qemu-devel@nongnu.org; Tue, 07 Apr 2009 18:28:53 -0400 Received: from [199.232.76.173] (port=33782 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LrJmn-0004Fv-C3 for qemu-devel@nongnu.org; Tue, 07 Apr 2009 18:28:53 -0400 Received: from savannah.gnu.org ([199.232.41.3]:35871 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LrJmm-0007J2-QY for qemu-devel@nongnu.org; Tue, 07 Apr 2009 18:28:52 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1LrJml-0000At-NT for qemu-devel@nongnu.org; Tue, 07 Apr 2009 22:28:51 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.69) (envelope-from ) id 1LrJml-0000Af-4R for qemu-devel@nongnu.org; Tue, 07 Apr 2009 22:28:51 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Tue, 07 Apr 2009 22:28:51 +0000 Subject: [Qemu-devel] [7031] mc146818: add square wave output support Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 7031 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=7031 Author: aurel32 Date: 2009-04-07 22:28:50 +0000 (Tue, 07 Apr 2009) Log Message: ----------- mc146818: add square wave output support This is necessary for es40 as the sqw output is directly connected to the core chipset. Signed-off-by: Tristan Gingold Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/hw/mc146818rtc.c trunk/hw/pc.h Modified: trunk/hw/mc146818rtc.c =================================================================== --- trunk/hw/mc146818rtc.c 2009-04-07 22:03:44 UTC (rev 7030) +++ trunk/hw/mc146818rtc.c 2009-04-07 22:28:50 UTC (rev 7031) @@ -50,11 +50,12 @@ #define REG_A_UIP 0x80 -#define REG_B_SET 0x80 -#define REG_B_PIE 0x40 -#define REG_B_AIE 0x20 -#define REG_B_UIE 0x10 -#define REG_B_DM 0x04 +#define REG_B_SET 0x80 +#define REG_B_PIE 0x40 +#define REG_B_AIE 0x20 +#define REG_B_UIE 0x10 +#define REG_B_SQWE 0x08 +#define REG_B_DM 0x04 struct RTCState { uint8_t cmos_data[128]; @@ -62,6 +63,7 @@ struct tm current_tm; int base_year; qemu_irq irq; + qemu_irq sqw_irq; int it_shift; /* periodic timer */ QEMUTimer *periodic_timer; @@ -95,16 +97,20 @@ { int period_code, period; int64_t cur_clock, next_irq_clock; + int enable_pie; period_code = s->cmos_data[RTC_REG_A] & 0x0f; #if defined TARGET_I386 || defined TARGET_X86_64 /* disable periodic timer if hpet is in legacy mode, since interrupts are * disabled anyway. */ - if (period_code != 0 && (s->cmos_data[RTC_REG_B] & REG_B_PIE) && !hpet_in_legacy_mode()) { + enable_pie = hpet_in_legacy_mode(); #else - if (period_code != 0 && (s->cmos_data[RTC_REG_B] & REG_B_PIE)) { + enable_pie = 1; #endif + if (period_code != 0 + && (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie) + || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) { if (period_code <= 2) period_code += 7; /* period in 32 Khz cycles */ @@ -138,8 +144,15 @@ return; } #endif - s->cmos_data[RTC_REG_C] |= 0xc0; - rtc_irq_raise(s->irq); + if (s->cmos_data[RTC_REG_B] & REG_B_PIE) { + s->cmos_data[RTC_REG_C] |= 0xc0; + rtc_irq_raise(s->irq); + } + if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) { + /* Not square wave at all but we don't want 2048Hz interrupts! + Must be seen as a pulse. */ + qemu_irq_raise(s->sqw_irq); + } } static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) @@ -527,13 +540,14 @@ } #endif -RTCState *rtc_init(int base, qemu_irq irq, int base_year) +RTCState *rtc_init_sqw(int base, qemu_irq irq, qemu_irq sqw_irq, int base_year) { RTCState *s; s = qemu_mallocz(sizeof(RTCState)); s->irq = irq; + s->sqw_irq = sqw_irq; s->cmos_data[RTC_REG_A] = 0x26; s->cmos_data[RTC_REG_B] = 0x02; s->cmos_data[RTC_REG_C] = 0x00; @@ -563,6 +577,11 @@ return s; } +RTCState *rtc_init(int base, qemu_irq irq, int base_year) +{ + return rtc_init_sqw(base, irq, NULL, base_year); +} + /* Memory mapped interface */ static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr) { Modified: trunk/hw/pc.h =================================================================== --- trunk/hw/pc.h 2009-04-07 22:03:44 UTC (rev 7030) +++ trunk/hw/pc.h 2009-04-07 22:28:50 UTC (rev 7031) @@ -90,6 +90,7 @@ typedef struct RTCState RTCState; RTCState *rtc_init(int base, qemu_irq irq, int base_year); +RTCState *rtc_init_sqw(int base, qemu_irq irq, qemu_irq sqw_irq, int base_year); RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, int base_year); void rtc_set_memory(RTCState *s, int addr, int val);