[Qemu-devel] [7096] target-mips: fix commits 7040 and 7042

[Qemu-devel] [7096] target-mips: fix commits 7040 and 7042

[Aurelien Jarno]

Revision: 7096
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=7096
Author:   aurel32
Date:     2009-04-13 08:53:12 +0000 (Mon, 13 Apr 2009)
Log Message:
-----------
target-mips: fix commits 7040 and 7042

CPU state should also be saved for helpers that in fine call
cpu_unlink_tb(). Reported by Stefan Weil.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

Modified Paths:
--------------
    trunk/target-mips/translate.c

Modified: trunk/target-mips/translate.c
===================================================================
--- trunk/target-mips/translate.c	2009-04-12 08:32:45 UTC (rev 7095)
+++ trunk/target-mips/translate.c	2009-04-13 08:53:12 UTC (rev 7096)
@@ -3697,6 +3697,7 @@
     case 12:
         switch (sel) {
         case 0:
+            save_cpu_state(ctx, 1);
             gen_helper_mtc0_status(t0);
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx->pc + 4);
@@ -3731,6 +3732,7 @@
     case 13:
         switch (sel) {
         case 0:
+            save_cpu_state(ctx, 1);
             gen_helper_mtc0_cause(t0);
             rn = "Cause";
             break;
@@ -4861,6 +4863,7 @@
     case 12:
         switch (sel) {
         case 0:
+            save_cpu_state(ctx, 1);
             gen_helper_mtc0_status(t0);
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx->pc + 4);
@@ -4895,14 +4898,13 @@
     case 13:
         switch (sel) {
         case 0:
+            save_cpu_state(ctx, 1);
             gen_helper_mtc0_cause(t0);
             rn = "Cause";
             break;
         default:
             goto die;
         }
-        /* Stop translation as we may have switched the execution mode */
-        ctx->bstate = BS_STOP;
         break;
     case 14:
         switch (sel) {
@@ -7972,6 +7974,7 @@
                     break;
                 case OPC_DI:
                     check_insn(env, ctx, ISA_MIPS32R2);
+                    save_cpu_state(ctx, 1);
                     gen_helper_di(t0);
                     gen_store_gpr(t0, rt);
                     /* Stop translation as we may have switched the execution mode */
@@ -7979,6 +7982,7 @@
                     break;
                 case OPC_EI:
                     check_insn(env, ctx, ISA_MIPS32R2);
+                    save_cpu_state(ctx, 1);
                     gen_helper_ei(t0);
                     gen_store_gpr(t0, rt);
                     /* Stop translation as we may have switched the execution mode */