From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LuQ7n-0006hT-Ty for qemu-devel@nongnu.org; Thu, 16 Apr 2009 07:51:24 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LuQ7m-0006gs-CV for qemu-devel@nongnu.org; Thu, 16 Apr 2009 07:51:22 -0400 Received: from [199.232.76.173] (port=51795 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LuQ7k-0006gX-HE for qemu-devel@nongnu.org; Thu, 16 Apr 2009 07:51:21 -0400 Received: from savannah.gnu.org ([199.232.41.3]:40482 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LuQ7k-0003Dp-7N for qemu-devel@nongnu.org; Thu, 16 Apr 2009 07:51:20 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1LuQ7j-0004EH-OR for qemu-devel@nongnu.org; Thu, 16 Apr 2009 11:51:19 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.69) (envelope-from ) id 1LuQ7j-0004ED-Ex for qemu-devel@nongnu.org; Thu, 16 Apr 2009 11:51:19 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Thu, 16 Apr 2009 11:51:19 +0000 Subject: [Qemu-devel] [7127] target-mips: fix call to check_*() functions Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 7127 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=7127 Author: aurel32 Date: 2009-04-16 11:51:19 +0000 (Thu, 16 Apr 2009) Log Message: ----------- target-mips: fix call to check_*() functions check_*() functions may in fine call generate_exception(), which ends by a call to tcg_gen_exit_tb(). As a consequence, we have to make sure that no TCG temp variables are crossing a check_*() function. Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/target-mips/translate.c Modified: trunk/target-mips/translate.c =================================================================== --- trunk/target-mips/translate.c 2009-04-16 11:51:11 UTC (rev 7126) +++ trunk/target-mips/translate.c 2009-04-16 11:51:19 UTC (rev 7127) @@ -6382,10 +6382,13 @@ TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); + if (ctx->opcode & (1 << 6)) { + check_cop1x(ctx); + } + gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); if (ctx->opcode & (1 << 6)) { - check_cop1x(ctx); gen_cmpabs_s(func-48, fp0, fp1, cc); opn = condnames_abs[func-48]; } else { @@ -6744,16 +6747,17 @@ { TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp1 = tcg_temp_new_i64(); + if (ctx->opcode & (1 << 6)) { + check_cop1x(ctx); + } + check_cp1_registers(ctx, fs | ft); gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); if (ctx->opcode & (1 << 6)) { - check_cop1x(ctx); - check_cp1_registers(ctx, fs | ft); gen_cmpabs_d(func-48, fp0, fp1, cc); opn = condnames_abs[func-48]; } else { - check_cp1_registers(ctx, fs | ft); gen_cmp_d(func-48, fp0, fp1, cc); opn = condnames[func-48]; } @@ -7222,6 +7226,22 @@ int store = 0; TCGv t0 = tcg_temp_new(); + switch (opc) { + case OPC_LWXC1: + case OPC_SWXC1: + check_cop1x(ctx); + break; + case OPC_LDXC1: + case OPC_SDXC1: + check_cop1x(ctx); + check_cp1_registers(ctx, fd); + break; + case OPC_LUXC1: + case OPC_SUXC1: + check_cp1_64bitmode(ctx); + break; + } + if (base == 0) { gen_load_gpr(t0, index); } else if (index == 0) { @@ -7235,7 +7255,6 @@ save_cpu_state(ctx, 0); switch (opc) { case OPC_LWXC1: - check_cop1x(ctx); { TCGv_i32 fp0 = tcg_temp_new_i32(); @@ -7247,8 +7266,6 @@ opn = "lwxc1"; break; case OPC_LDXC1: - check_cop1x(ctx); - check_cp1_registers(ctx, fd); { TCGv_i64 fp0 = tcg_temp_new_i64(); @@ -7259,7 +7276,6 @@ opn = "ldxc1"; break; case OPC_LUXC1: - check_cp1_64bitmode(ctx); tcg_gen_andi_tl(t0, t0, ~0x7); { TCGv_i64 fp0 = tcg_temp_new_i64(); @@ -7271,7 +7287,6 @@ opn = "luxc1"; break; case OPC_SWXC1: - check_cop1x(ctx); { TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv t1 = tcg_temp_new(); @@ -7286,8 +7301,6 @@ store = 1; break; case OPC_SDXC1: - check_cop1x(ctx); - check_cp1_registers(ctx, fs); { TCGv_i64 fp0 = tcg_temp_new_i64(); @@ -7299,7 +7312,6 @@ store = 1; break; case OPC_SUXC1: - check_cp1_64bitmode(ctx); tcg_gen_andi_tl(t0, t0, ~0x7); { TCGv_i64 fp0 = tcg_temp_new_i64();