From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MSYAv-0001BQ-7A for qemu-devel@nongnu.org; Sun, 19 Jul 2009 11:19:41 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MSYAt-0001Am-Un for qemu-devel@nongnu.org; Sun, 19 Jul 2009 11:19:40 -0400 Received: from [199.232.76.173] (port=55059 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MSYAt-0001Aj-Py for qemu-devel@nongnu.org; Sun, 19 Jul 2009 11:19:39 -0400 Received: from a40-prg1-8-129.static.adsl.vol.cz ([88.146.54.129]:53344 helo=FilipNavara-PC) by monty-python.gnu.org with smtp (Exim 4.60) (envelope-from ) id 1MSYAs-00030b-El for qemu-devel@nongnu.org; Sun, 19 Jul 2009 11:19:39 -0400 From: Filip Navara Sender: Filip Navara MIME-Version: 1.0 Content-Type: text/plain; Message-Id: Subject: [Qemu-devel] [PATCH 01/18] Use tcg_global_mem_new_i32 to allocate ARM registers in TCG. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Date: Sun, 19 Jul 2009 15:19:41 -0000 To: qemu-devel@nongnu.org Currently each read/write of ARM register involves a LD/ST TCG operation. This patch uses TCG memory-backed registers to represent the ARM register set. With memory-backed registers the LD/ST operations are transparently generated by TCG and host registers could be used to optimize the generated code. Signed-off-by: Filip Navara --- target-arm/translate.c | 40 +++++++++++++++++++++++----------------- 1 files changed, 23 insertions(+), 17 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index c32e7f9..a0c0436 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -76,6 +76,7 @@ typedef struct DisasContext { static TCGv_ptr cpu_env; /* We reuse the same 64-bit temporaries for efficiency. */ static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; +static TCGv_i32 cpu_R[16]; /* FIXME: These should be removed. */ static TCGv cpu_T[2]; @@ -85,14 +86,26 @@ static TCGv_i64 cpu_F0d, cpu_F1d; #define ICOUNT_TEMP cpu_T[0] #include "gen-icount.h" +static const char *regnames[] = + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; + /* initialize TCG globals. */ void arm_translate_init(void) { + int i; + cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); cpu_T[0] = tcg_global_reg_new_i32(TCG_AREG1, "T0"); cpu_T[1] = tcg_global_reg_new_i32(TCG_AREG2, "T1"); + for (i = 0; i < 16; i++) { + cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, regs[i]), + regnames[i]); + } + #define GEN_HELPER 2 #include "helpers.h" } @@ -167,7 +180,7 @@ static void load_reg_var(DisasContext *s, TCGv var, int reg) addr = (long)s->pc + 4; tcg_gen_movi_i32(var, addr); } else { - tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, regs[reg])); + tcg_gen_mov_i32(var, cpu_R[reg]); } } @@ -187,7 +200,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var) tcg_gen_andi_i32(var, var, ~1); s->is_jmp = DISAS_JUMP; } - tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, regs[reg])); + tcg_gen_mov_i32(cpu_R[reg], var); dead_tmp(var); } @@ -789,27 +802,22 @@ static inline void gen_bx_im(DisasContext *s, uint32_t addr) TCGv tmp; s->is_jmp = DISAS_UPDATE; - tmp = new_tmp(); if (s->thumb != (addr & 1)) { + tmp = new_tmp(); tcg_gen_movi_i32(tmp, addr & 1); tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb)); + dead_tmp(tmp); } - tcg_gen_movi_i32(tmp, addr & ~1); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, regs[15])); - dead_tmp(tmp); + tcg_gen_mov_i32(cpu_R[15], addr & ~1); } /* Set PC and Thumb state from var. var is marked as dead. */ static inline void gen_bx(DisasContext *s, TCGv var) { - TCGv tmp; - s->is_jmp = DISAS_UPDATE; - tmp = new_tmp(); - tcg_gen_andi_i32(tmp, var, 1); - store_cpu_field(tmp, thumb); - tcg_gen_andi_i32(var, var, ~1); - store_cpu_field(var, regs[15]); + tcg_gen_andi_i32(cpu_R[15], var, ~1); + tcg_gen_andi_i32(var, var, 1); + store_cpu_field(var, thumb); } /* Variant of store_reg which uses branch&exchange logic when storing @@ -888,9 +896,7 @@ static inline void gen_movl_T2_reg(DisasContext *s, int reg) static inline void gen_set_pc_im(uint32_t val) { - TCGv tmp = new_tmp(); - tcg_gen_movi_i32(tmp, val); - store_cpu_field(tmp, regs[15]); + tcg_gen_movi_i32(cpu_R[15], val); } static inline void gen_movl_reg_TN(DisasContext *s, int reg, int t) @@ -902,7 +908,7 @@ static inline void gen_movl_reg_TN(DisasContext *s, int reg, int t) } else { tmp = cpu_T[t]; } - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, regs[reg])); + tcg_gen_mov_i32(cpu_R[reg], tmp); if (reg == 15) { dead_tmp(tmp); s->is_jmp = DISAS_JUMP; -- 1.6.3.2.1299.gee46c