From: Filip Navara <filip.navara@gmail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 14/18] Convert disas_dsp_insn not use cpu_T.
Date: Sun, 19 Jul 2009 15:20:05 -0000 [thread overview]
Message-ID: <E1MSYBI-0001P4-Br@lists.gnu.org> (raw)
Signed-off-by: Filip Navara <filip.navara@gmail.com>
---
target-arm/translate.c | 59 ++++++++++++++++-------------------------------
1 files changed, 20 insertions(+), 39 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 6a57918..c7e417c 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -1302,21 +1302,6 @@ IWMMXT_OP_ENV(packsw)
IWMMXT_OP_ENV(packsl)
IWMMXT_OP_ENV(packsq)
-static inline void gen_op_iwmmxt_muladdsl_M0_T0_T1(void)
-{
- gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
-}
-
-static inline void gen_op_iwmmxt_muladdsw_M0_T0_T1(void)
-{
- gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
-}
-
-static inline void gen_op_iwmmxt_muladdswl_M0_T0_T1(void)
-{
- gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
-}
-
static inline void gen_op_iwmmxt_align_M0_T0_wRn(int rn)
{
iwmmxt_load_reg(cpu_V1, rn);
@@ -1381,7 +1366,6 @@ static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
}
-
static void gen_iwmmxt_movl_T0_T1_wRn(int rn)
{
iwmmxt_load_reg(cpu_V0, rn);
@@ -2382,12 +2366,12 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
case 0x0: /* TMIA */
gen_movl_T0_reg(s, rd0);
gen_movl_T1_reg(s, rd1);
- gen_op_iwmmxt_muladdsl_M0_T0_T1();
+ gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
break;
case 0x8: /* TMIAPH */
gen_movl_T0_reg(s, rd0);
gen_movl_T1_reg(s, rd1);
- gen_op_iwmmxt_muladdsw_M0_T0_T1();
+ gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
break;
case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
gen_movl_T1_reg(s, rd0);
@@ -2397,7 +2381,7 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
gen_movl_T1_reg(s, rd1);
if (insn & (1 << 17))
gen_op_shrl_T1_im(16);
- gen_op_iwmmxt_muladdswl_M0_T0_T1();
+ gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]);
break;
default:
return 1;
@@ -2417,6 +2401,7 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
{
int acc, rd0, rd1, rdhi, rdlo;
+ TCGv tmp, tmp2;
if ((insn & 0x0ff00f10) == 0x0e200010) {
/* Multiply with Internal Accumulate Format */
@@ -2427,33 +2412,30 @@ static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
if (acc != 0)
return 1;
+ tmp = load_reg(s, rd0);
+ tmp2 = load_reg(s, rd1);
switch ((insn >> 16) & 0xf) {
case 0x0: /* MIA */
- gen_movl_T0_reg(s, rd0);
- gen_movl_T1_reg(s, rd1);
- gen_op_iwmmxt_muladdsl_M0_T0_T1();
+ gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
break;
case 0x8: /* MIAPH */
- gen_movl_T0_reg(s, rd0);
- gen_movl_T1_reg(s, rd1);
- gen_op_iwmmxt_muladdsw_M0_T0_T1();
+ gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
break;
case 0xc: /* MIABB */
case 0xd: /* MIABT */
case 0xe: /* MIATB */
case 0xf: /* MIATT */
- gen_movl_T1_reg(s, rd0);
if (insn & (1 << 16))
- gen_op_shrl_T1_im(16);
- gen_op_movl_T0_T1();
- gen_movl_T1_reg(s, rd1);
+ tcg_gen_shri_i32(tmp, tmp, 16);
if (insn & (1 << 17))
- gen_op_shrl_T1_im(16);
- gen_op_iwmmxt_muladdswl_M0_T0_T1();
+ tcg_gen_shri_i32(tmp2, tmp2, 16);
+ gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
break;
default:
return 1;
}
+ dead_tmp(tmp2);
+ dead_tmp(tmp);
gen_op_iwmmxt_movq_wRn_M0(acc);
return 0;
@@ -2469,15 +2451,14 @@ static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
return 1;
if (insn & ARM_CP_RW_BIT) { /* MRA */
- gen_iwmmxt_movl_T0_T1_wRn(acc);
- gen_movl_reg_T0(s, rdlo);
- gen_op_movl_T0_im((1 << (40 - 32)) - 1);
- gen_op_andl_T0_T1();
- gen_movl_reg_T0(s, rdhi);
+ iwmmxt_load_reg(cpu_V0, acc);
+ tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
+ tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
+ tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
+ tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
} else { /* MAR */
- gen_movl_T0_reg(s, rdlo);
- gen_movl_T1_reg(s, rdhi);
- gen_iwmmxt_movl_wRn_T0_T1(acc);
+ tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
+ iwmmxt_store_reg(cpu_V0, acc);
}
return 0;
}
--
1.6.3.2.1299.gee46c
reply other threads:[~2009-07-19 15:20 UTC|newest]
Thread overview: [no followups] expand[flat|nested] mbox.gz Atom feed
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=E1MSYBI-0001P4-Br@lists.gnu.org \
--to=filip.navara@gmail.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).