From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MTGSl-00080J-J8 for qemu-devel@nongnu.org; Tue, 21 Jul 2009 10:37:03 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MTGSg-0007wd-QX for qemu-devel@nongnu.org; Tue, 21 Jul 2009 10:37:03 -0400 Received: from [199.232.76.173] (port=58487 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MTGSg-0007wG-Ij for qemu-devel@nongnu.org; Tue, 21 Jul 2009 10:36:58 -0400 Received: from [82.113.48.144] (port=61495 helo=FilipNavara-PC) by monty-python.gnu.org with smtp (Exim 4.60) (envelope-from ) id 1MTGSf-0000bi-Nu for qemu-devel@nongnu.org; Tue, 21 Jul 2009 10:36:58 -0400 From: Filip Navara Sender: Filip Navara MIME-Version: 1.0 Content-Type: text/plain; Message-Id: Subject: [Qemu-devel] [PATCH] RFC: TCG constant propagation. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Date: Tue, 21 Jul 2009 14:37:03 -0000 To: qemu-devel@nongnu.org Cc: @codesourcery.compaul@codesourcery.com, paul@codesourcery.compaul Add support for constant propagation to TCG. This has to be paired with the liveness analysis to remove the dead code. Not all possible operations are covered, but the most common ones are. This improves the code generation for several ARM instructions, like MVN (immediate), and it may help other targets as well. --- tcg/tcg.c | 164 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 164 insertions(+), 0 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 4cb5934..10b6a99 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1025,7 +1025,169 @@ void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs) #endif tdefs++; } +} + +static void tcg_const_analysis(TCGContext *s) +{ + int nb_cargs, nb_iargs, nb_oargs, dest, src, src2, del_args, i; + TCGArg *args; + uint16_t op; + uint16_t *opc_ptr; + const TCGOpDef *def; + uint8_t *const_temps; + tcg_target_ulong *temp_values; + tcg_target_ulong val, mask; + tcg_target_ulong dest_val, src_val, src2_val; + + const_temps = tcg_malloc(s->nb_temps); + memset(const_temps, 0, s->nb_temps); + temp_values = tcg_malloc(s->nb_temps * sizeof(uint32_t)); + + opc_ptr = gen_opc_buf; + args = gen_opparam_buf; + while (opc_ptr < gen_opc_ptr) { + op = *opc_ptr; + def = &tcg_op_defs[op]; + nb_oargs = def->nb_oargs; + nb_iargs = def->nb_iargs; + nb_cargs = def->nb_cargs; + del_args = 0; + mask = ~((tcg_target_ulong)0); + switch(op) { + case INDEX_op_movi_i32: +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_movi_i64: +#endif + dest = args[0]; + val = args[1]; + const_temps[dest] = 1; + temp_values[dest] = val; + break; + case INDEX_op_mov_i32: +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_mov_i64: +#endif + dest = args[0]; + src = args[1]; + const_temps[dest] = const_temps[src]; + temp_values[dest] = temp_values[src]; + break; + case INDEX_op_not_i32: +#if TCG_TARGET_REG_BITS == 64 + mask = 0xffffffff; + case INDEX_op_not_i64: +#endif + dest = args[0]; + src = args[1]; + if (const_temps[src]) { + const_temps[dest] = 1; + dest_val = ~temp_values[src]; + *opc_ptr = INDEX_op_movi_i32; + args[1] = temp_values[dest] = dest_val & mask; + } else { + const_temps[dest] = 0; + } + break; + case INDEX_op_add_i32: + case INDEX_op_sub_i32: + case INDEX_op_mul_i32: + case INDEX_op_and_i32: + case INDEX_op_or_i32: + case INDEX_op_xor_i32: + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: +#if TCG_TARGET_REG_BITS == 64 + mask = 0xffffffff; + case INDEX_op_add_i64: + case INDEX_op_sub_i64: + case INDEX_op_mul_i64: + case INDEX_op_and_i64: + case INDEX_op_or_i64: + case INDEX_op_xor_i64: + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: +#endif + + dest = args[0]; + src = args[1]; + src2 = args[2]; + if (const_temps[src] && const_temps[src2]) { + src_val = temp_values[src]; + src2_val = temp_values[src2]; + const_temps[dest] = 1; + switch (op) { + case INDEX_op_add_i32: + dest_val = src_val + src2_val; + break; + case INDEX_op_sub_i32: + dest_val = src_val - src2_val; + break; + case INDEX_op_mul_i32: + dest_val = src_val * src2_val; + break; + case INDEX_op_and_i32: + dest_val = src_val & src2_val; + break; + case INDEX_op_or_i32: + dest_val = src_val | src2_val; + break; + case INDEX_op_xor_i32: + dest_val = src_val ^ src2_val; + break; + case INDEX_op_shl_i32: + dest_val = src_val << src2_val; + break; + case INDEX_op_shr_i32: + dest_val = src_val >> src2_val; + break; + default: + tcg_abort(); + return; + } + *opc_ptr = INDEX_op_movi_i32; + args[1] = temp_values[dest] = dest_val & mask; + del_args = 1; + } else { + const_temps[dest] = 0; + } + break; + case INDEX_op_call: + nb_oargs = args[0] >> 16; + nb_iargs = args[0] & 0xffff; + nb_cargs = def->nb_cargs; + args++; + for (i = 0; i < nb_oargs; i++) { + const_temps[args[i]] = 0; + } + break; + case INDEX_op_nopn: + /* variable number of arguments */ + nb_cargs = args[0]; + break; + case INDEX_op_set_label: + memset(const_temps, 0, s->nb_temps); + break; + default: + if (def->flags & TCG_OPF_BB_END) { + memset(const_temps, 0, s->nb_temps); + } else { + for (i = 0; i < nb_oargs; i++) { + const_temps[args[i]] = 0; + } + } + break; + } + opc_ptr++; + args += nb_iargs + nb_oargs + nb_cargs - del_args; + if (del_args > 0) { + gen_opparam_ptr -= del_args; + memmove(args, args + del_args, (gen_opparam_ptr - args) * sizeof(*args)); + } + } + + if (args != gen_opparam_ptr) + tcg_abort(); } #ifdef USE_LIVENESS_ANALYSIS @@ -1895,6 +2057,8 @@ static inline int tcg_gen_code_common(TCGContext *s, uint8_t *gen_code_buf, } #endif + tcg_const_analysis(s); + #ifdef CONFIG_PROFILER s->la_time -= profile_getclock(); #endif -- 1.6.3.2.1299.gee46c