From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58226) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAxqu-0000r4-Px for qemu-devel@nongnu.org; Wed, 17 May 2017 08:15:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dAxqa-00073c-46 for qemu-devel@nongnu.org; Wed, 17 May 2017 08:14:52 -0400 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:36754) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dAxqZ-0006yL-HW for qemu-devel@nongnu.org; Wed, 17 May 2017 08:14:31 -0400 Received: by mail-wm0-x242.google.com with SMTP id k15so1750760wmh.3 for ; Wed, 17 May 2017 05:14:31 -0700 (PDT) From: Dmitry Fleytman Message-Id: Mime-Version: 1.0 (Mac OS X Mail 10.3 \(3273\)) Date: Wed, 17 May 2017 15:14:27 +0300 In-Reply-To: <1495021572-20852-1-git-send-email-sameeh@daynix.com> References: <1495021572-20852-1-git-send-email-sameeh@daynix.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] e1000e: Fix a bug where guest hangs upon migration List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sameeh Jubran Cc: Qemu Developers , Jason Wang , Yan Vugenfirer > On 17 May 2017, at 14:46 PM, Sameeh Jubran wrote: >=20 > The bug was caused by the "receive overrun" (bit #6 of the ICR = register) interrupt > which would be triggered post migration in a heavy traffic = environment. Even though the > "receive overrun" bit (#6) is masked out by the IMS register (refer to = the log below) > the driver still receives an interrupt as the "receive overrun" bit = (#6) causes the > "Other" - bit #24 of the ICR register - bit to be set as documented = below. The driver > handles the interrupt and clears the "Other" bit (#24) but doesn't = clear the > "receive overrun" bit (#6) which leads to an infinite loop. Apparently = the Windows > driver expects that the "receive overrun" bit and other ones - = documented below - to be > cleared when the "Other" bit (#24) is cleared. >=20 > So to sum that up: > 1. Bit #6 of the ICR register is set by heavy traffic > 2. As a results of setting bit #6, bit #24 is set > 3. The driver receives an interrupt for bit 24 (it doesn't receieve an = interrupt for bit #6 as it is masked out by IMS) > 4. The driver handles and clears the interrupt of bit #24 > 5. Bit #6 is still set. > 6. 2 happens all over again >=20 > The Interrupt Cause Read - ICR register: >=20 > The ICR has the "Other" bit - bit #24 - that is set when one or more = of the following > ICR register's bits are set: >=20 > LSC - bit #2, RXO - bit #6, MDAC - bit #9, SRPD - bit #16, ACK - bit = #17, MNG - bit #18 >=20 > Log sample of the storm: >=20 > 27563@1494850819.411877:e1000e_irq_pending_interrupts ICR PENDING: = 0x1000000 (ICR: 0x815000c2, IMS: 0x1a00004) > 27563@1494850819.411900:e1000e_irq_pending_interrupts ICR PENDING: 0x0 = (ICR: 0x815000c2, IMS: 0xa00004) > 27563@1494850819.411915:e1000e_irq_pending_interrupts ICR PENDING: 0x0 = (ICR: 0x815000c2, IMS: 0xa00004) > 27563@1494850819.412380:e1000e_irq_pending_interrupts ICR PENDING: 0x0 = (ICR: 0x815000c2, IMS: 0xa00004) > 27563@1494850819.412395:e1000e_irq_pending_interrupts ICR PENDING: 0x0 = (ICR: 0x815000c2, IMS: 0xa00004) > 27563@1494850819.412436:e1000e_irq_pending_interrupts ICR PENDING: 0x0 = (ICR: 0x815000c2, IMS: 0xa00004) > 27563@1494850819.412441:e1000e_irq_pending_interrupts ICR PENDING: 0x0 = (ICR: 0x815000c2, IMS: 0xa00004) > 27563@1494850819.412998:e1000e_irq_pending_interrupts ICR PENDING: = 0x1000000 (ICR: 0x815000c2, IMS: 0x1a00004) >=20 > This commit solves: > https://bugzilla.redhat.com/show_bug.cgi?id=3D1447935 > https://bugzilla.redhat.com/show_bug.cgi?id=3D1449490 = Reviewed-by: Dmitry Fleytman >=20 > Signed-off-by: Sameeh Jubran > --- > hw/net/e1000e_core.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) >=20 > diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c > index 28c5be1..8174b53 100644 > --- a/hw/net/e1000e_core.c > +++ b/hw/net/e1000e_core.c > @@ -2454,14 +2454,17 @@ e1000e_set_ics(E1000ECore *core, int index, = uint32_t val) > static void > e1000e_set_icr(E1000ECore *core, int index, uint32_t val) > { > + uint32_t icr =3D 0; > if ((core->mac[ICR] & E1000_ICR_ASSERTED) && > (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { > trace_e1000e_irq_icr_process_iame(); > e1000e_clear_ims_bits(core, core->mac[IAM]); > } >=20 > - trace_e1000e_irq_icr_write(val, core->mac[ICR], core->mac[ICR] & = ~val); > - core->mac[ICR] &=3D ~val; > + icr =3D core->mac[ICR] & ~val; > + icr =3D (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) = : icr; > + trace_e1000e_irq_icr_write(val, core->mac[ICR], icr); > + core->mac[ICR] =3D icr; > e1000e_update_interrupt_state(core); > } >=20 > --=20 > 2.8.1.185.gdc0db2c >=20