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From: malc <malc@pulsesoft.com>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] cvttps2dq, movdq2q, movq2dq incorrect behaviour
Date: Wed, 21 Jun 2006 15:04:26 +0400 (MSD)	[thread overview]
Message-ID: <Pine.LNX.4.64.0606211502190.2135@home.oyster.ru> (raw)
In-Reply-To: <Pine.LNX.4.64.0606211214070.698@home.oyster.ru>

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On Wed, 21 Jun 2006, malc wrote:

> On Wed, 21 Jun 2006, Julian Seward wrote:
>
>> 
>> Malc, your sse-movq.patch works for me.  Thanks.
>> 
>>> soft-float was a red herring, translate.c is at fault here (interpreter
>>> does not use it, hence behaved correctly)

[..snip..]

>>> 
>>> cvttps2dq is 0x5b(b=0x5b) with repn prefix (b1=2) the above code is
>>> optimized a bit more than it should have been, as it loads only 4 bytes
>>> into xmm_t0 instead of 16.
>> 
>> Uh, fine, but I don't understand how/what to fix.  Can you advise?
>
> Following will fix the _specific_ case of cvttps2dq, ideally one
> should go through all the [0x50..0x5f, 0xc2] with (repnz,repz prefix)
> range and check wether the rules imposed by the above snippet apply.

[..snip..]

>

It appears that cvttps2dq is indeed the only exception in the range,
combined patch that fixes both movd?q2d?q and cvttps2dq is attached.

I don't have any kind of SSE on this machine so would apprecaite if
someone would run tests/test-i386 with the patch attached.

--
mailto:malc@pulsesoft.com

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Index: target-i386/translate.c
===================================================================
RCS file: /cvsroot/qemu/qemu/target-i386/translate.c,v
retrieving revision 1.57
diff -u -u -r1.57 translate.c
--- target-i386/translate.c	14 Jun 2006 14:29:34 -0000	1.57
+++ target-i386/translate.c	21 Jun 2006 11:01:47 -0000
@@ -2947,15 +2947,15 @@
         case 0x2d6: /* movq2dq */
             gen_op_enter_mmx();
             rm = (modrm & 7) | REX_B(s);
-            gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
-                        offsetof(CPUX86State,fpregs[reg & 7].mmx));
-            gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
+            gen_op_movq(offsetof(CPUX86State,xmm_regs[reg & 7].XMM_Q(0)),
+                        offsetof(CPUX86State,fpregs[rm].mmx));
+            gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg & 7].XMM_Q(1)));
             break;
         case 0x3d6: /* movdq2q */
             gen_op_enter_mmx();
             rm = (modrm & 7);
-            gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
-                        offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+            gen_op_movq(offsetof(CPUX86State,fpregs[reg].mmx),
+                        offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
             break;
         case 0xd7: /* pmovmskb */
         case 0x1d7:
@@ -3006,8 +3006,9 @@
             if (mod != 3) {
                 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
                 op2_offset = offsetof(CPUX86State,xmm_t0);
-                if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f) ||
-                                b == 0xc2)) {
+                if (!(b1 == 2 && b == 0x5b) &&
+                    (b1 >= 2 && ((b >= 0x50 && b <= 0x5f) ||
+                                b == 0xc2))) {
                     /* specific case for SSE single instructions */
                     if (b1 == 2) {
                         /* 32 bit access */

  reply	other threads:[~2006-06-21 11:04 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2006-06-20 10:54 [Qemu-devel] cvttps2dq, movdq2q, movq2dq incorrect behaviour Julian Seward
2006-06-20 11:29 ` malc
2006-06-20 11:48   ` Julian Seward
2006-06-20 14:26     ` malc
2006-06-21  0:31       ` Julian Seward
2006-06-21  8:21         ` malc
2006-06-21 11:04           ` malc [this message]
2006-06-21 23:01             ` Julian Seward
2006-06-20 13:15 ` RE : " Sylvain Petreolle
2006-06-20 13:51   ` malc
2006-06-20 14:13     ` Julian Seward
2006-06-20 15:06       ` RE : " Sylvain Petreolle
2006-06-20 15:14         ` Guillaume POIRIER
2006-06-20 14:17     ` RE : " Jens Axboe
2006-06-20 14:23       ` Jens Axboe

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