Re: [Qemu-devel] Pending MIPS patches

[Marius Groeger <mgroeger@sysgo.com>]

On Sun, 25 Jun 2006, Fabrice Bellard wrote:

>>  2. [PATCH][MIPS] add "lwu" instruction
>>  http://lists.gnu.org/archive/html/qemu-devel/2006-04/msg00326.html
>
> On which MIPS CPU is it defined ? Need to track instruction sets exactly to 
> be able to select a given MIPS CPU at compile time or dynamically.

Since the initial patch came from me: "lwu" is part of MIPS III.

>>  4. [PATCH][MIPS] Enforce aligned pc
>>  http://lists.gnu.org/archive/html/qemu-devel/2006-04/msg00484.html
>
> Can it happen on a real MIPS ? If not, an assert should be used for example.

Again this is one of mine. Yes, it can happen. You're free to load any 
crap into the link register GPR31. The documentation of "JR - jump 
register" says:

   If these low-order bits are not zero, an address exception will
   occur when the jump target instruction is subsequently fetched.

BTW, I'm referring to the document

   64-Bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture
   Rev 1.0

The TX49 uses an R4K core.

Regards,
Marius

-- 
Marius Groeger <mgroeger@sysgo.com>
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