From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1FunVP-00041Y-1h for qemu-devel@nongnu.org; Mon, 26 Jun 2006 05:35:43 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1FunVN-00040a-Tv for qemu-devel@nongnu.org; Mon, 26 Jun 2006 05:35:42 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1FunVN-00040U-Jr for qemu-devel@nongnu.org; Mon, 26 Jun 2006 05:35:41 -0400 Received: from [62.8.134.5] (helo=mail.sysgo.com) by monty-python.gnu.org with esmtp (Exim 4.52) id 1FunhD-00017b-P2 for qemu-devel@nongnu.org; Mon, 26 Jun 2006 05:47:56 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.sysgo.com (Postfix) with ESMTP id AB3FBFB84C for ; Mon, 26 Jun 2006 11:35:37 +0200 (CEST) Received: from donald.sysgo.com (unknown [172.20.1.30]) by mail.sysgo.com (Postfix) with ESMTP id 9E544FB84C for ; Mon, 26 Jun 2006 11:35:37 +0200 (CEST) Received: from localhost (unknown [172.25.1.18]) by donald.sysgo.com (Postfix) with ESMTP id EFF7F268579 for ; Mon, 26 Jun 2006 11:35:34 +0200 (CEST) Date: Mon, 26 Jun 2006 11:35:34 +0200 (CEST) From: Marius Groeger Sender: mag@sysgo.com Subject: Re: [Qemu-devel] Pending MIPS patches In-Reply-To: <449EBC39.3050701@bellard.org> Message-ID: References: <449EB5FA.6070405@gmail.com> <449EBC39.3050701@bellard.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Sun, 25 Jun 2006, Fabrice Bellard wrote: >> 2. [PATCH][MIPS] add "lwu" instruction >> http://lists.gnu.org/archive/html/qemu-devel/2006-04/msg00326.html > > On which MIPS CPU is it defined ? Need to track instruction sets exactly to > be able to select a given MIPS CPU at compile time or dynamically. Since the initial patch came from me: "lwu" is part of MIPS III. >> 4. [PATCH][MIPS] Enforce aligned pc >> http://lists.gnu.org/archive/html/qemu-devel/2006-04/msg00484.html > > Can it happen on a real MIPS ? If not, an assert should be used for example. Again this is one of mine. Yes, it can happen. You're free to load any crap into the link register GPR31. The documentation of "JR - jump register" says: If these low-order bits are not zero, an address exception will occur when the jump target instruction is subsequently fetched. BTW, I'm referring to the document 64-Bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture Rev 1.0 The TX49 uses an R4K core. Regards, Marius -- Marius Groeger SYSGO AG Embedded and Real-Time Software Voice: +49 6136 9948 0 FAX: +49 6136 9948 10 www.sysgo.com | www.elinos.com | www.osek.de | www.pikeos.com