From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1H9Hba-0004ef-Cm for qemu-devel@nongnu.org; Tue, 23 Jan 2007 04:06:14 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1H9HbY-0004dq-7z for qemu-devel@nongnu.org; Tue, 23 Jan 2007 04:06:12 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1H9HbX-0004db-Rf for qemu-devel@nongnu.org; Tue, 23 Jan 2007 04:06:11 -0500 Received: from [62.8.134.5] (helo=mail.sysgo.com) by monty-python.gnu.org with esmtp (Exim 4.52) id 1H9HbX-0003Fz-6i for qemu-devel@nongnu.org; Tue, 23 Jan 2007 04:06:11 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.sysgo.com (Postfix) with ESMTP id CF6F8CC152 for ; Tue, 23 Jan 2007 10:06:08 +0100 (CET) Received: from donald.sysgo.com (unknown [172.20.1.30]) by mail.sysgo.com (Postfix) with ESMTP id 89776CC14D for ; Tue, 23 Jan 2007 10:06:08 +0100 (CET) Received: from mag-lap.sysgo.com (mag-lap.sysgo.com [172.24.2.132]) by donald.sysgo.com (Postfix) with ESMTP id 56195284D78 for ; Tue, 23 Jan 2007 10:06:08 +0100 (CET) Date: Tue, 23 Jan 2007 10:06:07 +0100 (CET) From: Marius Groeger Sender: mag@sysgo.com Subject: Re: [Qemu-devel] [RFC] IRQ acknowledge on MIPS In-Reply-To: <20070123004819.GA10927@amd64.aurel32.net> Message-ID: References: <20070123004819.GA10927@amd64.aurel32.net> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Tue, 23 Jan 2007, Aurelien Jarno wrote: > There is currently a bug concerning the IRQ acknowlege on the MIPS > system emulation. It concerns both the QEMU and Malta boards, though it > is only detectable with a 2.4 kernel and thus on the Malta board. The > symptom is a storm of "We got a spurious interrupt from PIIX4." > > This is due to the kernel requesting the interrupt number from the > i8259A where no interrupt is waiting. In such a case the i8259A answers > by an IRQ 7. > > When an hardware interrupt occurs, the i8259A memorizes the interrupt > and sends it to the MIPS CPU. This is done via the pic_irq_request() > function. The result is that the bit 10 of the CP0 Cause register is > set to one (interrupt 2). But when the interrupt is finished, the i8259a > registers IRR and ISR are cleared, but not the CP0 Cause register. The > CPU always thinks there is an interrupt to serve, which is wrong. I can confirm this issue. For our (custom) OS I worked around this by manualy clearing CP0 Cause (even though I think I shouldn't be allowed to do that since CP0:IP[7-2] are read-only, but that's another story... ;-) > Does anyone has an idea of a sane implementation for that? It seems > only the MIPS platform has to clear a register of the CPU when an > interrupt is finished. What about passing another hook to pic_init which, if set, would be called when no more interrupts are pending? Would that be too specific this problem to be an acceptable solution? Regards, Marius -- Marius Groeger SYSGO AG Embedded and Real-Time Software Voice: +49 6136 9948 0 FAX: +49 6136 9948 10 www.sysgo.com | www.elinos.com | www.osek.de | www.pikeos.com