From: malc <av1474@comtv.ru>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] SSE 'maxps' instruction bug?
Date: Mon, 12 Mar 2007 19:27:23 +0300 (MSK) [thread overview]
Message-ID: <Pine.LNX.4.64.0703121921580.14408@linmac.oyster.ru> (raw)
In-Reply-To: <200703121450.41180.jseward@acm.org>
On Mon, 12 Mar 2007, Julian Seward wrote:
>
> The program below tests the 'maxps' instruction. When run on
> qemu-0.9.0, host amd64, guest x86, guest OS redhat8, it prints:
>
> f9a511d1 8d37d67f b34825b8 e2f40739
>
> scp the binary to a Core 2 (real) machine and run:
>
> f9a511d1 22dcb9b9 b34825b8 e2f40739
>
> Second 32-bit word is completely different.
>
> This is 0.9.0 compiled from source using gcc-3.4.6, host openSuSE
> 10.2 on a Core 2 Duo in 64-bit mode.
>
> Any ideas? I grepped the 0.9.0 sources for "maxps" but couldn't
> figure out where/how it is handled.
[..snip..]
ops_sse.h lines 711 and 670
QEMU and Core 2 Duo disagree on the handling of NaNs it seems.
http://courses.ece.uiuc.edu/ece390/books/labmanual/inst-ref-simd.html
- this implies that MAXPS should leave the NaNs alone, no idea how
normative that is though (and no IA32 manual at hand)
--
vale
next prev parent reply other threads:[~2007-03-12 16:29 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-03-12 14:50 [Qemu-devel] SSE 'maxps' instruction bug? Julian Seward
2007-03-12 16:27 ` malc [this message]
2007-03-13 14:03 ` Julian Seward
2007-03-13 23:07 ` Tim Olson
2007-03-14 2:21 ` Julian Seward
2007-03-16 18:07 ` Rob Landley
2007-03-16 18:10 ` Julian Seward
2007-03-16 20:17 ` Rob Landley
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