From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LsXY2-00063y-Mm for qemu-devel@nongnu.org; Sat, 11 Apr 2009 03:22:42 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LsXY1-00062V-NK for qemu-devel@nongnu.org; Sat, 11 Apr 2009 03:22:42 -0400 Received: from [199.232.76.173] (port=56481 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LsXY1-00062F-8v for qemu-devel@nongnu.org; Sat, 11 Apr 2009 03:22:41 -0400 Received: from fe01x03-cgp.akado.ru ([77.232.31.164]:63580 helo=akado.ru) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LsXY0-0002mw-RA for qemu-devel@nongnu.org; Sat, 11 Apr 2009 03:22:41 -0400 Date: Sat, 11 Apr 2009 11:22:40 +0400 (MSD) From: malc In-Reply-To: Message-ID: References: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Subject: [Qemu-devel] Re: [RFC] OSX/ppc64 TCG support Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?ISO-8859-1?Q?Andreas_F=E4rber?= Cc: qemu-devel On Sat, 11 Apr 2009, Andreas F?rber wrote: > Hello, > > I've tried to add TCG backend support for Mac OS X ppc64 with limited success. > It seems the linkage area and LR offset are the same as on Linux, so the main > difference I could find was the register usage. > > This brought up two questions: > > i) In ppc/tcg-target.c TCG_REG_R2 is listed twice in > tcg_target_reg_alloc_order for __APPLE__. I assume this is not intended? It > does so far work with or without this patch eliminating the second use: Not intended, thanks for noticing. > > diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c > index 23f94a8..7607d85 100644 > --- a/tcg/ppc/tcg-target.c > +++ b/tcg/ppc/tcg-target.c > @@ -114,7 +114,9 @@ static const int tcg_target_reg_alloc_order[] = { > #endif > TCG_REG_R0, > TCG_REG_R1, > +#ifndef __APPLE__ > TCG_REG_R2, > +#endif > TCG_REG_R24, > TCG_REG_R25, > TCG_REG_R26, > > Alternatively, if the order of r2 does not matter too much, we could > remove the initial __APPLE__ section instead for simplicity. > > ii) In ppc64/tcg-target.c tcg_target_call_oarg_regs is declared with a > length of 2 but only contains one register. Intended? Probably not, then again i'd have to recheck PPC64 ABI for DI/struct returns to be sure, then again QEMU doesn't sue those. Anyhow... > diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c > index a96314c..2a8eaec 100644 > --- a/tcg/ppc64/tcg-target.c > +++ b/tcg/ppc64/tcg-target.c > @@ -125,11 +134,15 @@ static const int tcg_target_call_iarg_regs[] = { > TCG_REG_R10 > }; > > -static const int tcg_target_call_oarg_regs[2] = { > +static const int tcg_target_call_oarg_regs[1] = { > TCG_REG_R3 > }; This is most certainly is just as in correct as having it at [2] and not initializing element N1 since main tcg proper never invokes ARRAY_SIZE on tcg_target_call_oarg_regs... > > Then for the real OSX/ppc64 changes, I have marked r11 and r13 > callee-saved, like for OSX/ppc. Reference: > http://developer.apple.com/documentation/DeveloperTools/Conceptual/LowLevelABI/110-64-bit_PowerPC_Function_Calling_Conventions/64bitPowerPC.html > > To my knowledge in ppc64 mode (at least on the G5) the lmw and stmw > instructions are illegal. We should probably remove their definitions, they > are not currently being used in the ppc64 backend. They aren't used in PPC32 case either, i'll whack them. > Unfortunately qemu-system-ppc still crashes immediately, any hints welcome. > > Program received signal EXC_BAD_INSTRUCTION, Illegal instruction/operand. > 0x00000000005a9680 in code_gen_prologue () > (gdb) bt I think TOCs are a lot different in ppc-elf64abi and Mach-O one, that would explain why it fails so early > #0 0x00000000005a9680 in code_gen_prologue () [..snip..] Unfortunatelly i don't have access to MacOSX on a PPC64 so you are on your own there. -- mailto:av1474@comtv.ru