* [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups
@ 2025-12-24 1:41 Kane Chen via
2025-12-24 1:41 ` [PATCH v4 01/19] hw/misc: Add LTPI controller Kane Chen via
` (20 more replies)
0 siblings, 21 replies; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Hi all,
LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP DC-SCM
2.0 specification (see Figure 2):
https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
LTPI provides a protocol and physical interface for tunneling various
low-speed signals between the Host Processor Module (HPM) and the
Satellite Controller Module (SCM). In Figure 2 of the specification,
the AST27x0 SoC (left) integrates two LTPI controllers, allowing it to
connect to up to two AST1700 boards. On the other side, the AST1700
consolidates HPM FPGA functions and multiple peripheral interfaces
(GPIO, UART, I2C, I3C, etc.) onto a single board.
Because the AST1700 exposes additional I/O interfaces (GPIO, I2C, I3C,
and others), it acts as an I/O expander. Once connected over LTPI,
the AST27x0 can control additional downstream devices through this link.
This patch series is based on the SGPIO changes:
https://patchwork.kernel.org/project/qemu-devel/patch/20251219-aspeed-sgpio-v5-1-fd5593178144@google.com/
It introduces a basic LTPI controller model and wires it into the
AST27x0 SoC. The series also adds the AST1700-specific LTPI expander
device and incrementally connects common peripherals on the AST1700
model. For the I3C block, which may cause kernel crashes, its MMIO
region is modeled as an unimplemented device to reserve address space
and make the missing functionality explicit, ensuring stable guest
probing.
In the official release images, the AST1700 functions are not included
by default. To test the AST1700-related functionality, please include
the following DTS files for probing:
https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-ltpi0.dtsi
https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-ltpi1.dtsi
After including these DTS files in the BMC image, you can verify LTPI
functionality using the following scenarios:
1. In U-Boot:
Run the ltpi command to trigger the LTPI connection and display the
current connection status.
2. In BMC Linux:
Run i2cdetect -y <16-38> to scan and test the I2C buses exposed by
the AST1700.
Any feedback or suggestions are appreciated!
Kane
---
ChangeLog
---------
v4:
- Add missing Signed-off-by
- Fix checkpatch.pl warnings
- Refine code structure
- Enable AST1700 support only after all devices are ready
v3:
- Add PWM model
- Integrate the SGPIO model
- Fix I2C test case failure
- Refine code structure
v2:
- Separate the AST1700 model into a standalone implementation
- Refine the mechanism for assigning the AST1700 board number
v1:
- Initial version
---
Kane-Chen-AS (19):
hw/misc: Add LTPI controller
hw/arm/aspeed: Attach LTPI controller to AST27X0 platform
hw/misc: Add basic Aspeed PWM model
hw/arm/aspeed: Add AST1700 LTPI expander device model
hw/arm/aspeed: Integrate AST1700 device into AST27X0
hw/arm/aspeed: Integrate interrupt controller for AST1700
hw/arm/aspeed: Attach LTPI controller to AST1700 model
hw/arm/aspeed: Attach UART device to AST1700 model
hw/arm/aspeed: Attach SRAM device to AST1700 model
hw/arm/aspeed: Attach SPI device to AST1700 model
hw/arm/aspeed: Attach ADC device to AST1700 model
hw/arm/aspeed: Attach SCU device to AST1700 model
hw/arm/aspeed: Attach GPIO device to AST1700 model
hw/arm/aspeed: attach I2C device to AST1700 model
hw/arm/aspeed: Attach WDT device to AST1700 model
hw/arm/aspeed: Attach PWM device to AST1700 model
hw/arm/aspeed: Attach SGPIOM device to AST1700 model
hw/arm/aspeed: Model AST1700 I3C block as unimplemented device
hw/arm/aspeed: Enable AST1700 IO expander support
include/hw/arm/aspeed_ast1700.h | 53 +++++++
include/hw/arm/aspeed_soc.h | 25 ++-
include/hw/i2c/aspeed_i2c.h | 1 +
include/hw/intc/aspeed_intc.h | 2 +
include/hw/misc/aspeed_ltpi.h | 33 ++++
include/hw/misc/aspeed_pwm.h | 31 ++++
hw/arm/aspeed_ast1700.c | 268 ++++++++++++++++++++++++++++++++
hw/arm/aspeed_ast27x0.c | 165 ++++++++++++++++++--
hw/i2c/aspeed_i2c.c | 19 ++-
hw/intc/aspeed_intc.c | 60 +++++++
hw/misc/aspeed_ltpi.c | 193 +++++++++++++++++++++++
hw/misc/aspeed_pwm.c | 121 ++++++++++++++
hw/arm/meson.build | 1 +
hw/misc/meson.build | 2 +
hw/misc/trace-events | 4 +
15 files changed, 959 insertions(+), 19 deletions(-)
create mode 100644 include/hw/arm/aspeed_ast1700.h
create mode 100644 include/hw/misc/aspeed_ltpi.h
create mode 100644 include/hw/misc/aspeed_pwm.h
create mode 100644 hw/arm/aspeed_ast1700.c
create mode 100644 hw/misc/aspeed_ltpi.c
create mode 100644 hw/misc/aspeed_pwm.c
--
2.43.0
^ permalink raw reply [flat|nested] 74+ messages in thread
* [PATCH v4 01/19] hw/misc: Add LTPI controller
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-24 10:36 ` Cédric Le Goater
2025-12-24 1:41 ` [PATCH v4 02/19] hw/arm/aspeed: Attach LTPI controller to AST27X0 platform Kane Chen via
` (19 subsequent siblings)
20 siblings, 1 reply; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP DC-SCM
2.0 specification:
https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
LTPI is a protocol and physical interface for tunneling various low-speed
signals between the HPM and SCM. As shown in Figure 2, the AST27x0 (left)
integrates two LTPI controllers, allowing it to connect to up to two
extended boards.
This commit introduces a simple device model for the ASPEED LTPI
controller in QEMU.
The model includes basic MMIO read/write operations and sets default
register values during reset to emulate a link-up state.
Implements register space with read/write callbacks.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/misc/aspeed_ltpi.h | 33 ++++++
hw/misc/aspeed_ltpi.c | 193 ++++++++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
3 files changed, 227 insertions(+)
create mode 100644 include/hw/misc/aspeed_ltpi.h
create mode 100644 hw/misc/aspeed_ltpi.c
diff --git a/include/hw/misc/aspeed_ltpi.h b/include/hw/misc/aspeed_ltpi.h
new file mode 100644
index 0000000000..e991afc666
--- /dev/null
+++ b/include/hw/misc/aspeed_ltpi.h
@@ -0,0 +1,33 @@
+/*
+ * ASPEED LTPI Controller
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef ASPEED_LTPI_H
+#define ASPEED_LTPI_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ASPEED_LTPI "aspeed.ltpi-ctrl"
+OBJECT_DECLARE_SIMPLE_TYPE(AspeedLTPIState, ASPEED_LTPI)
+
+#define ASPEED_LTPI_TOTAL_SIZE 0x900
+#define ASPEED_LTPI_CTRL_SIZE 0x200
+#define ASPEED_LTPI_PHY_SIZE 0x100
+#define ASPEED_LTPI_TOP_SIZE 0x100
+
+struct AspeedLTPIState {
+ SysBusDevice parent;
+ MemoryRegion mmio;
+ MemoryRegion mmio_ctrl;
+ MemoryRegion mmio_phy;
+ MemoryRegion mmio_top;
+
+ uint32_t ctrl_regs[ASPEED_LTPI_CTRL_SIZE >> 2];
+ uint32_t phy_regs[ASPEED_LTPI_PHY_SIZE >> 2];
+ uint32_t top_regs[ASPEED_LTPI_TOP_SIZE >> 2];
+};
+
+#endif /* ASPEED_LTPI_H */
diff --git a/hw/misc/aspeed_ltpi.c b/hw/misc/aspeed_ltpi.c
new file mode 100644
index 0000000000..131cea9c6b
--- /dev/null
+++ b/hw/misc/aspeed_ltpi.c
@@ -0,0 +1,193 @@
+/*
+ * ASPEED LTPI Controller
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "migration/vmstate.h"
+#include "hw/misc/aspeed_ltpi.h"
+
+#define ASPEED_LTPI_CTRL_BASE 0x000
+#define ASPEED_LTPI_PHY_BASE 0x200
+#define ASPEED_LTPI_TOP_BASE 0x800
+
+#define LTPI_CTRL_LINK_MNG 0x42
+#define LTPI_PHY_MODE 0x0
+
+static uint64_t aspeed_ltpi_top_read(void *opaque, hwaddr offset, unsigned size)
+{
+ AspeedLTPIState *s = opaque;
+ uint32_t idx = offset >> 2;
+
+ return s->top_regs[idx];
+}
+
+static void aspeed_ltpi_top_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AspeedLTPIState *s = opaque;
+ uint32_t idx = offset >> 2;
+
+ switch (offset) {
+ default:
+ s->top_regs[idx] = (uint32_t)val;
+ break;
+ }
+}
+
+static const MemoryRegionOps aspeed_ltpi_top_ops = {
+ .read = aspeed_ltpi_top_read,
+ .write = aspeed_ltpi_top_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static uint64_t aspeed_ltpi_phy_read(void *opaque, hwaddr offset, unsigned size)
+{
+ AspeedLTPIState *s = opaque;
+ uint32_t idx = offset >> 2;
+
+ return s->phy_regs[idx];
+}
+
+static void aspeed_ltpi_phy_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AspeedLTPIState *s = opaque;
+ uint32_t idx = offset >> 2;
+
+ switch (offset) {
+ default:
+ s->phy_regs[idx] = (uint32_t)val;
+ break;
+ }
+}
+
+static const MemoryRegionOps aspeed_ltpi_phy_ops = {
+ .read = aspeed_ltpi_phy_read,
+ .write = aspeed_ltpi_phy_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static uint64_t aspeed_ltpi_ctrl_read(void *opaque,
+ hwaddr offset, unsigned size)
+{
+ AspeedLTPIState *s = opaque;
+ uint32_t idx = offset >> 2;
+
+ return s->ctrl_regs[idx];
+}
+
+static void aspeed_ltpi_ctrl_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AspeedLTPIState *s = opaque;
+ uint32_t idx = offset >> 2;
+
+ switch (offset) {
+ default:
+ s->ctrl_regs[idx] = (uint32_t)val;
+ break;
+ }
+}
+
+static const MemoryRegionOps aspeed_ltpi_ctrl_ops = {
+ .read = aspeed_ltpi_ctrl_read,
+ .write = aspeed_ltpi_ctrl_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static void aspeed_ltpi_reset(DeviceState *dev)
+{
+ AspeedLTPIState *s = ASPEED_LTPI(dev);
+
+ memset(s->ctrl_regs, 0, sizeof(s->ctrl_regs));
+ memset(s->phy_regs, 0, sizeof(s->phy_regs));
+ memset(s->top_regs, 0, sizeof(s->top_regs));
+ /* set default values */
+ s->ctrl_regs[LTPI_CTRL_LINK_MNG] = 0x11900007;
+ s->phy_regs[LTPI_PHY_MODE] = 0x2;
+}
+
+
+static const VMStateDescription vmstate_aspeed_ltpi = {
+ .name = TYPE_ASPEED_LTPI,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(ctrl_regs, AspeedLTPIState,
+ ASPEED_LTPI_CTRL_SIZE >> 2),
+ VMSTATE_UINT32_ARRAY(phy_regs, AspeedLTPIState,
+ ASPEED_LTPI_PHY_SIZE >> 2),
+ VMSTATE_UINT32_ARRAY(top_regs, AspeedLTPIState,
+ ASPEED_LTPI_TOP_SIZE >> 2),
+
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void aspeed_ltpi_realize(DeviceState *dev, Error **errp)
+{
+ AspeedLTPIState *s = ASPEED_LTPI(dev);
+
+ memory_region_init(&s->mmio, OBJECT(s), TYPE_ASPEED_LTPI,
+ ASPEED_LTPI_TOTAL_SIZE);
+
+ memory_region_init_io(&s->mmio_ctrl, OBJECT(s),
+ &aspeed_ltpi_ctrl_ops, s,
+ "aspeed-ltpi-ctrl", ASPEED_LTPI_CTRL_SIZE);
+
+ memory_region_init_io(&s->mmio_phy, OBJECT(s),
+ &aspeed_ltpi_phy_ops, s,
+ "aspeed-ltpi-phy", ASPEED_LTPI_PHY_SIZE);
+
+ memory_region_init_io(&s->mmio_top, OBJECT(s),
+ &aspeed_ltpi_top_ops, s,
+ "aspeed-ltpi-top", ASPEED_LTPI_TOP_SIZE);
+
+ memory_region_add_subregion(&s->mmio,
+ ASPEED_LTPI_CTRL_BASE, &s->mmio_ctrl);
+ memory_region_add_subregion(&s->mmio,
+ ASPEED_LTPI_PHY_BASE, &s->mmio_phy);
+ memory_region_add_subregion(&s->mmio,
+ ASPEED_LTPI_TOP_BASE, &s->mmio_top);
+
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+}
+
+static void aspeed_ltpi_class_init(ObjectClass *klass, const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->realize = aspeed_ltpi_realize;
+ dc->vmsd = &vmstate_aspeed_ltpi;
+ device_class_set_legacy_reset(dc, aspeed_ltpi_reset);
+}
+
+static const TypeInfo aspeed_ltpi_info = {
+ .name = TYPE_ASPEED_LTPI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AspeedLTPIState),
+ .class_init = aspeed_ltpi_class_init,
+};
+
+static void aspeed_ltpi_register_types(void)
+{
+ type_register_static(&aspeed_ltpi_info);
+}
+
+type_init(aspeed_ltpi_register_types);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index b1d8d8e5d2..45b16e7797 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -136,6 +136,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_hace.c',
'aspeed_i3c.c',
'aspeed_lpc.c',
+ 'aspeed_ltpi.c',
'aspeed_scu.c',
'aspeed_sbc.c',
'aspeed_sdmc.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 02/19] hw/arm/aspeed: Attach LTPI controller to AST27X0 platform
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
2025-12-24 1:41 ` [PATCH v4 01/19] hw/misc: Add LTPI controller Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-29 19:37 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 03/19] hw/misc: Add basic Aspeed PWM model Kane Chen via
` (18 subsequent siblings)
20 siblings, 1 reply; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS, Cédric Le Goater
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the LTPI controller device (representing the AST1700 I/O
expander) to the AST27X0 SoC model. This patch sets up the memory
mapping and device registration according to the AST2700 SoC design,
where the LTPI controller is exposed at fixed MMIO regions.
This change only handles device instantiation and integration,
without implementing the controller's internal logic.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_soc.h | 5 +++++
hw/arm/aspeed_ast27x0.c | 21 +++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 18ff961a38..bca10c387b 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -43,6 +43,7 @@
#include "hw/fsi/aspeed_apb2opb.h"
#include "hw/char/serial-mm.h"
#include "hw/intc/arm_gicv3.h"
+#include "hw/misc/aspeed_ltpi.h"
#define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
@@ -55,6 +56,7 @@
#define ASPEED_UARTS_NUM 13
#define ASPEED_JTAG_NUM 2
#define ASPEED_PCIE_NUM 3
+#define ASPEED_IOEXP_NUM 2
struct AspeedSoCState {
DeviceState parent;
@@ -112,6 +114,7 @@ struct AspeedSoCState {
UnimplementedDeviceState ltpi;
UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
AspeedAPB2OPBState fsi[2];
+ AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM];
};
#define TYPE_ASPEED_SOC "aspeed-soc"
@@ -279,6 +282,8 @@ enum {
ASPEED_GIC_REDIST,
ASPEED_DEV_IPC0,
ASPEED_DEV_IPC1,
+ ASPEED_DEV_LTPI_CTRL1,
+ ASPEED_DEV_LTPI_CTRL2,
};
const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 70be3871bb..341b53189b 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -88,6 +88,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_UART10] = 0x14C33900,
[ASPEED_DEV_UART11] = 0x14C33A00,
[ASPEED_DEV_UART12] = 0x14C33B00,
+ [ASPEED_DEV_LTPI_CTRL1] = 0x14C34000,
+ [ASPEED_DEV_LTPI_CTRL2] = 0x14C35000,
[ASPEED_DEV_WDT] = 0x14C37000,
[ASPEED_DEV_LTPI] = 0x30000000,
[ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
@@ -556,6 +558,11 @@ static void aspeed_soc_ast2700_init(Object *obj)
object_property_set_int(OBJECT(&s->pcie[i]), "id", i, &error_abort);
}
+ for (i = 0; i < ASPEED_IOEXP_NUM; i++) {
+ object_initialize_child(obj, "ltpi-ctrl[*]",
+ &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI);
+ }
+
object_initialize_child(obj, "dpmcu", &s->dpmcu,
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "ltpi", &s->ltpi,
@@ -1047,6 +1054,20 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
return;
}
+ /* LTPI controller */
+ for (i = 0; i < ASPEED_IOEXP_NUM; i++) {
+ AspeedLTPIState *ltpi_ctrl;
+ hwaddr ltpi_base;
+
+ ltpi_ctrl = ASPEED_LTPI(&s->ltpi_ctrl[i]);
+ ltpi_base = sc->memmap[ASPEED_DEV_LTPI_CTRL1 + i];
+
+ if (!sysbus_realize(SYS_BUS_DEVICE(ltpi_ctrl), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base);
+ }
+
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
"aspeed.dpmcu",
sc->memmap[ASPEED_DEV_DPMCU],
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 03/19] hw/misc: Add basic Aspeed PWM model
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
2025-12-24 1:41 ` [PATCH v4 01/19] hw/misc: Add LTPI controller Kane Chen via
2025-12-24 1:41 ` [PATCH v4 02/19] hw/arm/aspeed: Attach LTPI controller to AST27X0 platform Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-24 10:37 ` Cédric Le Goater
2025-12-24 1:41 ` [PATCH v4 04/19] hw/arm/aspeed: Add AST1700 LTPI expander device model Kane Chen via
` (17 subsequent siblings)
20 siblings, 1 reply; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Add an initial PWM model for Aspeed SoCs, including device state,
register definitions, and basic initialization as a sysbus device.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 3 +-
include/hw/misc/aspeed_pwm.h | 31 +++++++++
hw/misc/aspeed_pwm.c | 121 +++++++++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
hw/misc/trace-events | 4 ++
5 files changed, 159 insertions(+), 1 deletion(-)
create mode 100644 include/hw/misc/aspeed_pwm.h
create mode 100644 hw/misc/aspeed_pwm.c
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index bca10c387b..7b08cca908 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -28,6 +28,7 @@
#include "hw/misc/aspeed_hace.h"
#include "hw/misc/aspeed_sbc.h"
#include "hw/misc/aspeed_sli.h"
+#include "hw/misc/aspeed_pwm.h"
#include "hw/watchdog/wdt_aspeed.h"
#include "hw/net/ftgmac100.h"
#include "target/arm/cpu.h"
@@ -88,6 +89,7 @@ struct AspeedSoCState {
MemoryRegion secsram;
UnimplementedDeviceState sbc_unimplemented;
AspeedSDMCState sdmc;
+ AspeedPWMState pwm;
AspeedWDTState wdt[ASPEED_WDTS_NUM];
FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
AspeedMiiState mii[ASPEED_MACS_NUM];
@@ -108,7 +110,6 @@ struct AspeedSoCState {
UnimplementedDeviceState video;
UnimplementedDeviceState emmc_boot_controller;
UnimplementedDeviceState dpmcu;
- UnimplementedDeviceState pwm;
UnimplementedDeviceState espi;
UnimplementedDeviceState udc;
UnimplementedDeviceState ltpi;
diff --git a/include/hw/misc/aspeed_pwm.h b/include/hw/misc/aspeed_pwm.h
new file mode 100644
index 0000000000..13dc3ea45b
--- /dev/null
+++ b/include/hw/misc/aspeed_pwm.h
@@ -0,0 +1,31 @@
+/*
+ * ASPEED PWM Controller
+ *
+ * Copyright (C) 2017-2021 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#ifndef ASPEED_PWM_H
+#define ASPEED_PWM_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ASPEED_PWM "aspeed.pwm"
+#define ASPEED_PWM(obj) OBJECT_CHECK(AspeedPWMState, (obj), TYPE_ASPEED_PWM)
+
+#define ASPEED_PWM_NR_REGS (0x10C >> 2)
+
+typedef struct AspeedPWMState {
+ /* <private> */
+ SysBusDevice parent;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ qemu_irq irq;
+
+ uint32_t regs[ASPEED_PWM_NR_REGS];
+} AspeedPWMState;
+
+#endif /* _ASPEED_PWM_H_ */
diff --git a/hw/misc/aspeed_pwm.c b/hw/misc/aspeed_pwm.c
new file mode 100644
index 0000000000..de209274af
--- /dev/null
+++ b/hw/misc/aspeed_pwm.c
@@ -0,0 +1,121 @@
+/*
+ * ASPEED PWM Controller
+ *
+ * Copyright (C) 2017-2021 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "hw/misc/aspeed_pwm.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
+
+#include "trace.h"
+
+static uint64_t aspeed_pwm_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ AspeedPWMState *s = ASPEED_PWM(opaque);
+ uint64_t val = 0;
+
+ addr >>= 2;
+
+ if (addr >= ASPEED_PWM_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr << 2);
+ } else {
+ val = s->regs[addr];
+ }
+
+ trace_aspeed_pwm_read(addr << 2, val);
+
+ return val;
+}
+
+static void aspeed_pwm_write(void *opaque, hwaddr addr, uint64_t data,
+ unsigned int size)
+{
+ AspeedPWMState *s = ASPEED_PWM(opaque);
+
+ trace_aspeed_pwm_write(addr, data);
+
+ addr >>= 2;
+
+ if (addr >= ASPEED_PWM_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr << 2);
+ return;
+ }
+
+ s->regs[addr] = data;
+}
+
+static const MemoryRegionOps aspeed_pwm_ops = {
+ .read = aspeed_pwm_read,
+ .write = aspeed_pwm_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static void aspeed_pwm_reset(DeviceState *dev)
+{
+ struct AspeedPWMState *s = ASPEED_PWM(dev);
+
+ memset(s->regs, 0, sizeof(s->regs));
+}
+
+static void aspeed_pwm_realize(DeviceState *dev, Error **errp)
+{
+ AspeedPWMState *s = ASPEED_PWM(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ sysbus_init_irq(sbd, &s->irq);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_pwm_ops, s,
+ TYPE_ASPEED_PWM, 0x1000);
+
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription vmstate_aspeed_pwm = {
+ .name = TYPE_ASPEED_PWM,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, AspeedPWMState, ASPEED_PWM_NR_REGS),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static void aspeed_pwm_class_init(ObjectClass *klass, const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = aspeed_pwm_realize;
+ device_class_set_legacy_reset(dc, aspeed_pwm_reset);
+ dc->desc = "Aspeed PWM Controller";
+ dc->vmsd = &vmstate_aspeed_pwm;
+}
+
+static const TypeInfo aspeed_pwm_info = {
+ .name = TYPE_ASPEED_PWM,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AspeedPWMState),
+ .class_init = aspeed_pwm_class_init,
+};
+
+static void aspeed_pwm_register_types(void)
+{
+ type_register_static(&aspeed_pwm_info);
+}
+
+type_init(aspeed_pwm_register_types);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 45b16e7797..7afe1d0009 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -137,6 +137,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_i3c.c',
'aspeed_lpc.c',
'aspeed_ltpi.c',
+ 'aspeed_pwm.c',
'aspeed_scu.c',
'aspeed_sbc.c',
'aspeed_sdmc.c',
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index eeb9243898..f7870babba 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -299,6 +299,10 @@ aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64
aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64
aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
+# aspeed_pwm.c
+aspeed_pwm_read(uint64_t offset, uint64_t data) "read: offset 0x%" PRIx64 " data 0x%" PRIx64
+aspeed_pwm_write(uint64_t offset, uint64_t data) "write: offset 0x%" PRIx64 " data 0x%" PRIx64
+
# aspeed_sdmc.c
aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 04/19] hw/arm/aspeed: Add AST1700 LTPI expander device model
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (2 preceding siblings ...)
2025-12-24 1:41 ` [PATCH v4 03/19] hw/misc: Add basic Aspeed PWM model Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-24 10:38 ` Cédric Le Goater
2025-12-29 19:37 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 05/19] hw/arm/aspeed: Integrate AST1700 device into AST27X0 Kane Chen via
` (16 subsequent siblings)
20 siblings, 2 replies; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Introduce a minimal QEMU device model for the ASPEED AST1700, an
MCU-less I/O expander used in the LTPI topology defined by the
DC-SCM 2.0 specification (see figure 2):
https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
This initial implementation includes:
* Definition of aspeed.ast1700 as a SysBusDevice
* Setup of a basic memory region to reserve I/O space for future
peripheral modeling
This stub establishes the foundation for LTPI-related device emulation,
without implementing any functional peripherals at this stage.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/arm/aspeed_ast1700.h | 23 ++++++++++++++++
hw/arm/aspeed_ast1700.c | 47 +++++++++++++++++++++++++++++++++
hw/arm/meson.build | 1 +
3 files changed, 71 insertions(+)
create mode 100644 include/hw/arm/aspeed_ast1700.h
create mode 100644 hw/arm/aspeed_ast1700.c
diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
new file mode 100644
index 0000000000..2a95ebfe89
--- /dev/null
+++ b/include/hw/arm/aspeed_ast1700.h
@@ -0,0 +1,23 @@
+/*
+ * ASPEED AST1700 IO Expander
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef ASPEED_AST1700_H
+#define ASPEED_AST1700_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ASPEED_AST1700 "aspeed.ast1700"
+
+OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700)
+
+struct AspeedAST1700SoCState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+};
+
+#endif /* ASPEED_AST1700_H */
diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
new file mode 100644
index 0000000000..bb6ca2ce9e
--- /dev/null
+++ b/hw/arm/aspeed_ast1700.c
@@ -0,0 +1,47 @@
+/*
+ * ASPEED AST1700 IO Expander
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/boards.h"
+#include "hw/qdev-core.h"
+#include "qom/object.h"
+#include "hw/arm/aspeed_ast1700.h"
+
+#define AST2700_SOC_LTPI_SIZE 0x01000000
+
+static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
+{
+ AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ /* Occupy memory space for all controllers in AST1700 */
+ memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700,
+ AST2700_SOC_LTPI_SIZE);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = aspeed_ast1700_realize;
+}
+
+static const TypeInfo aspeed_ast1700_info = {
+ .name = TYPE_ASPEED_AST1700,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AspeedAST1700SoCState),
+ .class_init = aspeed_ast1700_class_init,
+};
+
+static void aspeed_ast1700_register_types(void)
+{
+ type_register_static(&aspeed_ast1700_info);
+}
+
+type_init(aspeed_ast1700_register_types);
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index aeaf654790..175942263d 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -70,6 +70,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast10x0_evb.c',
'fby35.c'))
arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
+ 'aspeed_ast1700.c',
'aspeed_ast27x0.c',
'aspeed_ast27x0_evb.c',
'aspeed_ast27x0-fc.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 05/19] hw/arm/aspeed: Integrate AST1700 device into AST27X0
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (3 preceding siblings ...)
2025-12-24 1:41 ` [PATCH v4 04/19] hw/arm/aspeed: Add AST1700 LTPI expander device model Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-29 19:37 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700 Kane Chen via
` (15 subsequent siblings)
20 siblings, 1 reply; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS, Cédric Le Goater
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the AST1700 device as a child of the AST27X0 model to reflect
its role in DC-SCM 2.0 LTPI-based architectures. This patch wires
the AST1700 device into the platform without introducing functional
peripherals.
This forms the base for LTPI expander emulation in QEMU using
AST27X0 as the host controller.
Note: ioexp_num is set to 0 at this stage. Once all related devices
and interrupts are fully implemented, ioexp_num will be updated to
its expected value. This ensures the machine remains functional at
every commit and avoids potential compiler or build issues.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_soc.h | 7 +++++--
hw/arm/aspeed_ast27x0.c | 26 ++++++++++++++++++--------
2 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 7b08cca908..f19bab3457 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -45,6 +45,7 @@
#include "hw/char/serial-mm.h"
#include "hw/intc/arm_gicv3.h"
#include "hw/misc/aspeed_ltpi.h"
+#include "hw/arm/aspeed_ast1700.h"
#define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
@@ -112,10 +113,10 @@ struct AspeedSoCState {
UnimplementedDeviceState dpmcu;
UnimplementedDeviceState espi;
UnimplementedDeviceState udc;
- UnimplementedDeviceState ltpi;
UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
AspeedAPB2OPBState fsi[2];
AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM];
+ AspeedAST1700SoCState ioexp[ASPEED_IOEXP_NUM];
};
#define TYPE_ASPEED_SOC "aspeed-soc"
@@ -178,6 +179,7 @@ struct AspeedSoCClass {
int macs_num;
int uarts_num;
int uarts_base;
+ int ioexp_num;
const int *irqmap;
const hwaddr *memmap;
uint32_t num_cpus;
@@ -190,7 +192,6 @@ enum {
ASPEED_DEV_IOMEM,
ASPEED_DEV_IOMEM0,
ASPEED_DEV_IOMEM1,
- ASPEED_DEV_LTPI,
ASPEED_DEV_UART0,
ASPEED_DEV_UART1,
ASPEED_DEV_UART2,
@@ -285,6 +286,8 @@ enum {
ASPEED_DEV_IPC1,
ASPEED_DEV_LTPI_CTRL1,
ASPEED_DEV_LTPI_CTRL2,
+ ASPEED_DEV_LTPI_IO0,
+ ASPEED_DEV_LTPI_IO1,
};
const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 341b53189b..de39a3e7eb 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -26,7 +26,6 @@
#define AST2700_SOC_IO_SIZE 0x00FE0000
#define AST2700_SOC_IOMEM_SIZE 0x01000000
#define AST2700_SOC_DPMCU_SIZE 0x00040000
-#define AST2700_SOC_LTPI_SIZE 0x01000000
static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_VBOOTROM] = 0x00000000,
@@ -91,7 +90,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_LTPI_CTRL1] = 0x14C34000,
[ASPEED_DEV_LTPI_CTRL2] = 0x14C35000,
[ASPEED_DEV_WDT] = 0x14C37000,
- [ASPEED_DEV_LTPI] = 0x30000000,
+ [ASPEED_DEV_LTPI_IO0] = 0x30000000,
+ [ASPEED_DEV_LTPI_IO1] = 0x50000000,
[ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
[ASPEED_DEV_PCIE_MMIO1] = 0x80000000,
[ASPEED_DEV_PCIE_MMIO2] = 0xA0000000,
@@ -563,10 +563,14 @@ static void aspeed_soc_ast2700_init(Object *obj)
&s->ltpi_ctrl[i], TYPE_ASPEED_LTPI);
}
+ for (i = 0; i < sc->ioexp_num; i++) {
+ /* AST1700 IOEXP */
+ object_initialize_child(obj, "ioexp[*]", &s->ioexp[i],
+ TYPE_ASPEED_AST1700);
+ }
+
object_initialize_child(obj, "dpmcu", &s->dpmcu,
TYPE_UNIMPLEMENTED_DEVICE);
- object_initialize_child(obj, "ltpi", &s->ltpi,
- TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "iomem", &s->iomem,
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "iomem0", &s->iomem0,
@@ -1068,14 +1072,19 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base);
}
+ /* IO Expander */
+ for (i = 0; i < sc->ioexp_num; i++) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0,
+ sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
+ }
+
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
"aspeed.dpmcu",
sc->memmap[ASPEED_DEV_DPMCU],
AST2700_SOC_DPMCU_SIZE);
- aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->ltpi),
- "aspeed.ltpi",
- sc->memmap[ASPEED_DEV_LTPI],
- AST2700_SOC_LTPI_SIZE);
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem),
"aspeed.io",
sc->memmap[ASPEED_DEV_IOMEM],
@@ -1143,6 +1152,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
sc->macs_num = 3;
sc->uarts_num = 13;
sc->num_cpus = 4;
+ sc->ioexp_num = 0;
sc->uarts_base = ASPEED_DEV_UART0;
sc->irqmap = aspeed_soc_ast2700a1_irqmap;
sc->memmap = aspeed_soc_ast2700_memmap;
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (4 preceding siblings ...)
2025-12-24 1:41 ` [PATCH v4 05/19] hw/arm/aspeed: Integrate AST1700 device into AST27X0 Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-24 10:39 ` Cédric Le Goater
2025-12-24 10:57 ` Cédric Le Goater
2025-12-24 1:41 ` [PATCH v4 07/19] hw/arm/aspeed: Attach LTPI controller to AST1700 model Kane Chen via
` (14 subsequent siblings)
20 siblings, 2 replies; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the AST1700 interrupt lines to the GIC in AST27X0, enabling
the propagation of AST1700-originated interrupts to the host SoC.
This patch does not implement interrupt sources in AST1700 itself,
only the wiring into AST27X0.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 6 +++-
include/hw/intc/aspeed_intc.h | 2 ++
hw/arm/aspeed_ast27x0.c | 37 +++++++++++++++++++++
hw/intc/aspeed_intc.c | 60 +++++++++++++++++++++++++++++++++++
4 files changed, 104 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index f19bab3457..b051d0eb3a 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -58,6 +58,7 @@
#define ASPEED_UARTS_NUM 13
#define ASPEED_JTAG_NUM 2
#define ASPEED_PCIE_NUM 3
+#define ASPEED_INTC_NUM 2
#define ASPEED_IOEXP_NUM 2
struct AspeedSoCState {
@@ -146,7 +147,8 @@ struct Aspeed27x0SoCState {
AspeedSoCState parent;
ARMCPU cpu[ASPEED_CPUS_NUM];
- AspeedINTCState intc[2];
+ AspeedINTCState intc[ASPEED_INTC_NUM];
+ AspeedINTCState intcioexp[ASPEED_IOEXP_NUM];
GICv3State gic;
MemoryRegion dram_empty;
};
@@ -288,6 +290,8 @@ enum {
ASPEED_DEV_LTPI_CTRL2,
ASPEED_DEV_LTPI_IO0,
ASPEED_DEV_LTPI_IO1,
+ ASPEED_DEV_IOEXP0_INTCIO,
+ ASPEED_DEV_IOEXP1_INTCIO,
};
const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 51288384a5..4565bbab84 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -15,6 +15,8 @@
#define TYPE_ASPEED_INTC "aspeed.intc"
#define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
#define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
+#define TYPE_ASPEED_2700_INTCIOEXP1 TYPE_ASPEED_INTC "ast2700-ioexp1"
+#define TYPE_ASPEED_2700_INTCIOEXP2 TYPE_ASPEED_INTC "ast2700-ioexp2"
#define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
#define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp"
#define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp"
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index de39a3e7eb..678d4eb6d9 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -91,7 +91,9 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_LTPI_CTRL2] = 0x14C35000,
[ASPEED_DEV_WDT] = 0x14C37000,
[ASPEED_DEV_LTPI_IO0] = 0x30000000,
+ [ASPEED_DEV_IOEXP0_INTCIO] = 0x30C18000,
[ASPEED_DEV_LTPI_IO1] = 0x50000000,
+ [ASPEED_DEV_IOEXP1_INTCIO] = 0x50C18000,
[ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
[ASPEED_DEV_PCIE_MMIO1] = 0x80000000,
[ASPEED_DEV_PCIE_MMIO2] = 0xA0000000,
@@ -511,6 +513,10 @@ static void aspeed_soc_ast2700_init(Object *obj)
object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC);
object_initialize_child(obj, "intcio", &a->intc[1],
TYPE_ASPEED_2700_INTCIO);
+ object_initialize_child(obj, "intcioexp0", &a->intcioexp[0],
+ TYPE_ASPEED_2700_INTCIOEXP1);
+ object_initialize_child(obj, "intcioexp1", &a->intcioexp[1],
+ TYPE_ASPEED_2700_INTCIOEXP2);
snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
object_initialize_child(obj, "adc", &s->adc, typename);
@@ -755,6 +761,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0,
sc->memmap[ASPEED_DEV_INTCIO]);
+ /* INTCIOEXP0 */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[0]), errp)) {
+ return;
+ }
+
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[0]), 0,
+ sc->memmap[ASPEED_DEV_IOEXP0_INTCIO]);
+
+ /* INTCIOEXP1 */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[1]), errp)) {
+ return;
+ }
+
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[1]), 0,
+ sc->memmap[ASPEED_DEV_IOEXP1_INTCIO]);
+
/* irq sources -> orgates -> INTC */
for (i = 0; i < ic->num_inpins; i++) {
qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
@@ -1079,6 +1101,21 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0,
sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
+
+ icio = ASPEED_INTC_GET_CLASS(&a->intcioexp[i]);
+ /* INTC_IOEXP internal: orgate[i] -> input[i] */
+ for (int j = 0; j < icio->num_inpins; j++) {
+ irq = qdev_get_gpio_in(DEVICE(&a->intcioexp[i]), j);
+ qdev_connect_gpio_out(DEVICE(&a->intcioexp[i].orgates[j]), 0,
+ irq);
+ }
+
+ /* INTC_IOEXP output[i] -> INTC0.orgate[0].input[i] */
+ for (int j = 0; j < icio->num_outpins; j++) {
+ irq = qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), j);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->intcioexp[i]), j,
+ irq);
+ }
}
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 5cd786dee6..a04005ee7c 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -924,6 +924,64 @@ static const TypeInfo aspeed_2700_intc_info = {
.class_init = aspeed_2700_intc_class_init,
};
+static AspeedINTCIRQ aspeed_2700_intcioexp2_irqs[ASPEED_INTC_MAX_INPINS] = {
+ {0, 8, 1, R_GICINT192_EN, R_GICINT192_STATUS},
+ {1, 9, 1, R_GICINT193_EN, R_GICINT193_STATUS},
+};
+
+static void aspeed_2700_intcioexp2_class_init(ObjectClass *klass,
+ const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
+
+ dc->desc = "ASPEED 2700 IOEXP2 INTC Controller";
+ aic->num_lines = 32;
+ aic->num_inpins = 2;
+ aic->num_outpins = 10;
+ aic->mem_size = 0x400;
+ aic->nr_regs = 0x58 >> 2;
+ aic->reg_offset = 0x100;
+ aic->reg_ops = &aspeed_intcio_ops;
+ aic->irq_table = aspeed_2700_intcioexp2_irqs;
+ aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcioexp2_irqs);
+}
+
+static const TypeInfo aspeed_2700_intcioexp2_info = {
+ .name = TYPE_ASPEED_2700_INTCIOEXP2,
+ .parent = TYPE_ASPEED_INTC,
+ .class_init = aspeed_2700_intcioexp2_class_init,
+};
+
+static AspeedINTCIRQ aspeed_2700_intcioexp1_irqs[ASPEED_INTC_MAX_INPINS] = {
+ {0, 6, 1, R_GICINT192_EN, R_GICINT192_STATUS},
+ {1, 7, 1, R_GICINT193_EN, R_GICINT193_STATUS},
+};
+
+static void aspeed_2700_intcioexp1_class_init(ObjectClass *klass,
+ const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
+
+ dc->desc = "ASPEED 2700 IOEXP1 INTC Controller";
+ aic->num_lines = 32;
+ aic->num_inpins = 2;
+ aic->num_outpins = 10;
+ aic->mem_size = 0x400;
+ aic->nr_regs = 0x58 >> 2;
+ aic->reg_offset = 0x100;
+ aic->reg_ops = &aspeed_intcio_ops;
+ aic->irq_table = aspeed_2700_intcioexp1_irqs;
+ aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcioexp1_irqs);
+}
+
+static const TypeInfo aspeed_2700_intcioexp1_info = {
+ .name = TYPE_ASPEED_2700_INTCIOEXP1,
+ .parent = TYPE_ASPEED_INTC,
+ .class_init = aspeed_2700_intcioexp1_class_init,
+};
+
static AspeedINTCIRQ aspeed_2700_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
{0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS},
{1, 1, 1, R_GICINT193_EN, R_GICINT193_STATUS},
@@ -1099,6 +1157,8 @@ static void aspeed_intc_register_types(void)
type_register_static(&aspeed_intc_info);
type_register_static(&aspeed_2700_intc_info);
type_register_static(&aspeed_2700_intcio_info);
+ type_register_static(&aspeed_2700_intcioexp1_info);
+ type_register_static(&aspeed_2700_intcioexp2_info);
type_register_static(&aspeed_2700ssp_intc_info);
type_register_static(&aspeed_2700ssp_intcio_info);
type_register_static(&aspeed_2700tsp_intc_info);
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 07/19] hw/arm/aspeed: Attach LTPI controller to AST1700 model
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (5 preceding siblings ...)
2025-12-24 1:41 ` [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700 Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-24 10:41 ` Cédric Le Goater
2025-12-24 1:41 ` [PATCH v4 08/19] hw/arm/aspeed: Attach UART device " Kane Chen via
` (13 subsequent siblings)
20 siblings, 1 reply; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the LTPI controller to the AST1700 model by mapping its MMIO
region.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/arm/aspeed_ast1700.h | 3 +++
hw/arm/aspeed_ast1700.c | 27 +++++++++++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
index 2a95ebfe89..b9ee4952d0 100644
--- a/include/hw/arm/aspeed_ast1700.h
+++ b/include/hw/arm/aspeed_ast1700.h
@@ -9,6 +9,7 @@
#define ASPEED_AST1700_H
#include "hw/sysbus.h"
+#include "hw/misc/aspeed_ltpi.h"
#define TYPE_ASPEED_AST1700 "aspeed.ast1700"
@@ -18,6 +19,8 @@ struct AspeedAST1700SoCState {
SysBusDevice parent_obj;
MemoryRegion iomem;
+
+ AspeedLTPIState ltpi;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
index bb6ca2ce9e..eeb586102f 100644
--- a/hw/arm/aspeed_ast1700.c
+++ b/hw/arm/aspeed_ast1700.c
@@ -14,6 +14,14 @@
#define AST2700_SOC_LTPI_SIZE 0x01000000
+enum {
+ ASPEED_AST1700_DEV_LTPI_CTRL,
+};
+
+static const hwaddr aspeed_ast1700_io_memmap[] = {
+ [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
+};
+
static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
{
AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
@@ -23,8 +31,26 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700,
AST2700_SOC_LTPI_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
+
+ /* LTPI controller */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_CTRL],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0));
}
+static void aspeed_ast1700_instance_init(Object *obj)
+{
+ AspeedAST1700SoCState *s = ASPEED_AST1700(obj);
+
+ /* LTPI controller */
+ object_initialize_child(obj, "ltpi-ctrl",
+ &s->ltpi, TYPE_ASPEED_LTPI);
+
+ return;
+}
static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -37,6 +63,7 @@ static const TypeInfo aspeed_ast1700_info = {
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(AspeedAST1700SoCState),
.class_init = aspeed_ast1700_class_init,
+ .instance_init = aspeed_ast1700_instance_init,
};
static void aspeed_ast1700_register_types(void)
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 08/19] hw/arm/aspeed: Attach UART device to AST1700 model
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (6 preceding siblings ...)
2025-12-24 1:41 ` [PATCH v4 07/19] hw/arm/aspeed: Attach LTPI controller to AST1700 model Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 09/19] hw/arm/aspeed: Attach SRAM " Kane Chen via
` (12 subsequent siblings)
20 siblings, 1 reply; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS, Cédric Le Goater
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the UART controller to the AST1700 model by mapping its MMIO
region.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_ast1700.h | 2 ++
hw/arm/aspeed_ast1700.c | 18 ++++++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
index b9ee4952d0..a0d6b3ae44 100644
--- a/include/hw/arm/aspeed_ast1700.h
+++ b/include/hw/arm/aspeed_ast1700.h
@@ -10,6 +10,7 @@
#include "hw/sysbus.h"
#include "hw/misc/aspeed_ltpi.h"
+#include "hw/char/serial-mm.h"
#define TYPE_ASPEED_AST1700 "aspeed.ast1700"
@@ -21,6 +22,7 @@ struct AspeedAST1700SoCState {
MemoryRegion iomem;
AspeedLTPIState ltpi;
+ SerialMM uart;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
index eeb586102f..f444582795 100644
--- a/hw/arm/aspeed_ast1700.c
+++ b/hw/arm/aspeed_ast1700.c
@@ -10,15 +10,18 @@
#include "hw/boards.h"
#include "hw/qdev-core.h"
#include "qom/object.h"
+#include "hw/qdev-properties.h"
#include "hw/arm/aspeed_ast1700.h"
#define AST2700_SOC_LTPI_SIZE 0x01000000
enum {
+ ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
};
static const hwaddr aspeed_ast1700_io_memmap[] = {
+ [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
};
@@ -32,6 +35,17 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
AST2700_SOC_LTPI_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
+ /* UART */
+ qdev_prop_set_uint8(DEVICE(&s->uart), "regshift", 2);
+ qdev_prop_set_uint32(DEVICE(&s->uart), "baudbase", 38400);
+ qdev_prop_set_uint8(DEVICE(&s->uart), "endianness", DEVICE_LITTLE_ENDIAN);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0));
+
/* LTPI controller */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
return;
@@ -45,6 +59,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
{
AspeedAST1700SoCState *s = ASPEED_AST1700(obj);
+ /* UART */
+ object_initialize_child(obj, "uart[*]", &s->uart,
+ TYPE_SERIAL_MM);
+
/* LTPI controller */
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 09/19] hw/arm/aspeed: Attach SRAM device to AST1700 model
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (7 preceding siblings ...)
2025-12-24 1:41 ` [PATCH v4 08/19] hw/arm/aspeed: Attach UART device " Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 10/19] hw/arm/aspeed: Attach SPI " Kane Chen via
` (11 subsequent siblings)
20 siblings, 1 reply; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS, Cédric Le Goater
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Map the SRAM device to AST1700 model
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_ast1700.h | 2 ++
hw/arm/aspeed_ast1700.c | 18 ++++++++++++++++++
hw/arm/aspeed_ast27x0.c | 1 +
3 files changed, 21 insertions(+)
diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
index a0d6b3ae44..23588f7a81 100644
--- a/include/hw/arm/aspeed_ast1700.h
+++ b/include/hw/arm/aspeed_ast1700.h
@@ -20,9 +20,11 @@ struct AspeedAST1700SoCState {
SysBusDevice parent_obj;
MemoryRegion iomem;
+ uint8_t board_idx;
AspeedLTPIState ltpi;
SerialMM uart;
+ MemoryRegion sram;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
index f444582795..cb07d94054 100644
--- a/hw/arm/aspeed_ast1700.c
+++ b/hw/arm/aspeed_ast1700.c
@@ -14,13 +14,16 @@
#include "hw/arm/aspeed_ast1700.h"
#define AST2700_SOC_LTPI_SIZE 0x01000000
+#define AST1700_SOC_SRAM_SIZE 0x00040000
enum {
+ ASPEED_AST1700_DEV_SRAM,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
};
static const hwaddr aspeed_ast1700_io_memmap[] = {
+ [ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
};
@@ -29,12 +32,21 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
{
AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ char dev_name[32];
/* Occupy memory space for all controllers in AST1700 */
memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700,
AST2700_SOC_LTPI_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
+ /* SRAM */
+ snprintf(dev_name, sizeof(dev_name), "aspeed.ioexp-sram.%d", s->board_idx);
+ memory_region_init_ram(&s->sram, OBJECT(s), dev_name,
+ AST1700_SOC_SRAM_SIZE, errp);
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SRAM],
+ &s->sram);
+
/* UART */
qdev_prop_set_uint8(DEVICE(&s->uart), "regshift", 2);
qdev_prop_set_uint32(DEVICE(&s->uart), "baudbase", 38400);
@@ -69,11 +81,17 @@ static void aspeed_ast1700_instance_init(Object *obj)
return;
}
+
+static const Property aspeed_ast1700_props[] = {
+ DEFINE_PROP_UINT8("board-idx", AspeedAST1700SoCState, board_idx, 0),
+};
+
static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = aspeed_ast1700_realize;
+ device_class_set_props(dc, aspeed_ast1700_props);
}
static const TypeInfo aspeed_ast1700_info = {
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 678d4eb6d9..f2418e0e45 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -1096,6 +1096,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
/* IO Expander */
for (i = 0; i < sc->ioexp_num; i++) {
+ qdev_prop_set_uint8(DEVICE(&s->ioexp[i]), "board-idx", i);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) {
return;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 10/19] hw/arm/aspeed: Attach SPI device to AST1700 model
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (8 preceding siblings ...)
2025-12-24 1:41 ` [PATCH v4 09/19] hw/arm/aspeed: Attach SRAM " Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 11/19] hw/arm/aspeed: Attach ADC " Kane Chen via
` (10 subsequent siblings)
20 siblings, 1 reply; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS, Cédric Le Goater
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the SPI device to AST1700 model.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_ast1700.h | 2 ++
hw/arm/aspeed_ast1700.c | 22 ++++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
index 23588f7a81..5b120dd11a 100644
--- a/include/hw/arm/aspeed_ast1700.h
+++ b/include/hw/arm/aspeed_ast1700.h
@@ -10,6 +10,7 @@
#include "hw/sysbus.h"
#include "hw/misc/aspeed_ltpi.h"
+#include "hw/ssi/aspeed_smc.h"
#include "hw/char/serial-mm.h"
#define TYPE_ASPEED_AST1700 "aspeed.ast1700"
@@ -25,6 +26,7 @@ struct AspeedAST1700SoCState {
AspeedLTPIState ltpi;
SerialMM uart;
MemoryRegion sram;
+ AspeedSMCState spi;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
index cb07d94054..fc09bb1aed 100644
--- a/hw/arm/aspeed_ast1700.c
+++ b/hw/arm/aspeed_ast1700.c
@@ -17,15 +17,19 @@
#define AST1700_SOC_SRAM_SIZE 0x00040000
enum {
+ ASPEED_AST1700_DEV_SPI0,
ASPEED_AST1700_DEV_SRAM,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
+ ASPEED_AST1700_DEV_SPI0_MEM,
};
static const hwaddr aspeed_ast1700_io_memmap[] = {
+ [ASPEED_AST1700_DEV_SPI0] = 0x00030000,
[ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
+ [ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
};
static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
@@ -58,6 +62,20 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12],
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0));
+ /* SPI */
+ object_property_set_link(OBJECT(&s->spi), "dram",
+ OBJECT(&s->iomem), errp);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 0));
+
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0_MEM],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 1));
+
/* LTPI controller */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
return;
@@ -75,6 +93,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
object_initialize_child(obj, "uart[*]", &s->uart,
TYPE_SERIAL_MM);
+ /* SPI */
+ object_initialize_child(obj, "ioexp-spi[*]", &s->spi,
+ "aspeed.spi0-ast2700");
+
/* LTPI controller */
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 11/19] hw/arm/aspeed: Attach ADC device to AST1700 model
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (9 preceding siblings ...)
2025-12-24 1:41 ` [PATCH v4 10/19] hw/arm/aspeed: Attach SPI " Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 12/19] hw/arm/aspeed: Attach SCU " Kane Chen via
` (9 subsequent siblings)
20 siblings, 1 reply; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS, Cédric Le Goater
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the ADC device to AST1700 model.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_ast1700.h | 2 ++
hw/arm/aspeed_ast1700.c | 14 ++++++++++++++
hw/arm/aspeed_ast27x0.c | 5 +++++
3 files changed, 21 insertions(+)
diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
index 5b120dd11a..0c1216c4ba 100644
--- a/include/hw/arm/aspeed_ast1700.h
+++ b/include/hw/arm/aspeed_ast1700.h
@@ -9,6 +9,7 @@
#define ASPEED_AST1700_H
#include "hw/sysbus.h"
+#include "hw/adc/aspeed_adc.h"
#include "hw/misc/aspeed_ltpi.h"
#include "hw/ssi/aspeed_smc.h"
#include "hw/char/serial-mm.h"
@@ -27,6 +28,7 @@ struct AspeedAST1700SoCState {
SerialMM uart;
MemoryRegion sram;
AspeedSMCState spi;
+ AspeedADCState adc;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
index fc09bb1aed..e4d206045f 100644
--- a/hw/arm/aspeed_ast1700.c
+++ b/hw/arm/aspeed_ast1700.c
@@ -19,6 +19,7 @@
enum {
ASPEED_AST1700_DEV_SPI0,
ASPEED_AST1700_DEV_SRAM,
+ ASPEED_AST1700_DEV_ADC,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
ASPEED_AST1700_DEV_SPI0_MEM,
@@ -27,6 +28,7 @@ enum {
static const hwaddr aspeed_ast1700_io_memmap[] = {
[ASPEED_AST1700_DEV_SPI0] = 0x00030000,
[ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
+ [ASPEED_AST1700_DEV_ADC] = 0x00C00000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
[ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
@@ -76,6 +78,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0_MEM],
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 1));
+ /* ADC */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_ADC],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->adc), 0));
+
/* LTPI controller */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
return;
@@ -97,6 +107,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
object_initialize_child(obj, "ioexp-spi[*]", &s->spi,
"aspeed.spi0-ast2700");
+ /* ADC */
+ object_initialize_child(obj, "ioexp-adc[*]", &s->adc,
+ "aspeed.adc-ast2700");
+
/* LTPI controller */
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index f2418e0e45..84ff8b5557 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -1117,6 +1117,11 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intcioexp[i]), j,
irq);
}
+
+ /* ADC */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].adc), 0,
+ aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ADC));
+
}
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 12/19] hw/arm/aspeed: Attach SCU device to AST1700 model
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (10 preceding siblings ...)
2025-12-24 1:41 ` [PATCH v4 11/19] hw/arm/aspeed: Attach ADC " Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 13/19] hw/arm/aspeed: Attach GPIO " Kane Chen via
` (8 subsequent siblings)
20 siblings, 1 reply; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS, Cédric Le Goater
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the SCU device to AST1700 model.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_ast1700.h | 3 +++
hw/arm/aspeed_ast1700.c | 17 +++++++++++++++++
hw/arm/aspeed_ast27x0.c | 2 ++
3 files changed, 22 insertions(+)
diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
index 0c1216c4ba..12c57145c6 100644
--- a/include/hw/arm/aspeed_ast1700.h
+++ b/include/hw/arm/aspeed_ast1700.h
@@ -9,6 +9,7 @@
#define ASPEED_AST1700_H
#include "hw/sysbus.h"
+#include "hw/misc/aspeed_scu.h"
#include "hw/adc/aspeed_adc.h"
#include "hw/misc/aspeed_ltpi.h"
#include "hw/ssi/aspeed_smc.h"
@@ -23,12 +24,14 @@ struct AspeedAST1700SoCState {
MemoryRegion iomem;
uint8_t board_idx;
+ uint32_t silicon_rev;
AspeedLTPIState ltpi;
SerialMM uart;
MemoryRegion sram;
AspeedSMCState spi;
AspeedADCState adc;
+ AspeedSCUState scu;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
index e4d206045f..6494a5c4eb 100644
--- a/hw/arm/aspeed_ast1700.c
+++ b/hw/arm/aspeed_ast1700.c
@@ -20,6 +20,7 @@ enum {
ASPEED_AST1700_DEV_SPI0,
ASPEED_AST1700_DEV_SRAM,
ASPEED_AST1700_DEV_ADC,
+ ASPEED_AST1700_DEV_SCU,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
ASPEED_AST1700_DEV_SPI0_MEM,
@@ -29,6 +30,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
[ASPEED_AST1700_DEV_SPI0] = 0x00030000,
[ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
[ASPEED_AST1700_DEV_ADC] = 0x00C00000,
+ [ASPEED_AST1700_DEV_SCU] = 0x00C02000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
[ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
@@ -86,6 +88,16 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_ADC],
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->adc), 0));
+ /* SCU */
+ qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
+ s->silicon_rev);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SCU],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->scu), 0));
+
/* LTPI controller */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
return;
@@ -111,6 +123,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
object_initialize_child(obj, "ioexp-adc[*]", &s->adc,
"aspeed.adc-ast2700");
+ /* SCU */
+ object_initialize_child(obj, "ioexp-scu[*]", &s->scu,
+ TYPE_ASPEED_2700_SCU);
+
/* LTPI controller */
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
@@ -120,6 +136,7 @@ static void aspeed_ast1700_instance_init(Object *obj)
static const Property aspeed_ast1700_props[] = {
DEFINE_PROP_UINT8("board-idx", AspeedAST1700SoCState, board_idx, 0),
+ DEFINE_PROP_UINT32("silicon-rev", AspeedAST1700SoCState, silicon_rev, 0),
};
static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 84ff8b5557..6b9ad328dc 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -573,6 +573,8 @@ static void aspeed_soc_ast2700_init(Object *obj)
/* AST1700 IOEXP */
object_initialize_child(obj, "ioexp[*]", &s->ioexp[i],
TYPE_ASPEED_AST1700);
+ qdev_prop_set_uint32(DEVICE(&s->ioexp[i]), "silicon-rev",
+ sc->silicon_rev);
}
object_initialize_child(obj, "dpmcu", &s->dpmcu,
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 13/19] hw/arm/aspeed: Attach GPIO device to AST1700 model
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (11 preceding siblings ...)
2025-12-24 1:41 ` [PATCH v4 12/19] hw/arm/aspeed: Attach SCU " Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 14/19] hw/arm/aspeed: attach I2C " Kane Chen via
` (7 subsequent siblings)
20 siblings, 1 reply; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS, Cédric Le Goater
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the GPIO controller to the AST1700 model by mapping its MMIO
region and wiring its interrupt line.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_ast1700.h | 2 ++
hw/arm/aspeed_ast1700.c | 14 ++++++++++++++
hw/arm/aspeed_ast27x0.c | 4 ++++
3 files changed, 20 insertions(+)
diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
index 12c57145c6..7ea6ff4c1a 100644
--- a/include/hw/arm/aspeed_ast1700.h
+++ b/include/hw/arm/aspeed_ast1700.h
@@ -11,6 +11,7 @@
#include "hw/sysbus.h"
#include "hw/misc/aspeed_scu.h"
#include "hw/adc/aspeed_adc.h"
+#include "hw/gpio/aspeed_gpio.h"
#include "hw/misc/aspeed_ltpi.h"
#include "hw/ssi/aspeed_smc.h"
#include "hw/char/serial-mm.h"
@@ -32,6 +33,7 @@ struct AspeedAST1700SoCState {
AspeedSMCState spi;
AspeedADCState adc;
AspeedSCUState scu;
+ AspeedGPIOState gpio;
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
index 6494a5c4eb..9a6019908e 100644
--- a/hw/arm/aspeed_ast1700.c
+++ b/hw/arm/aspeed_ast1700.c
@@ -21,6 +21,7 @@ enum {
ASPEED_AST1700_DEV_SRAM,
ASPEED_AST1700_DEV_ADC,
ASPEED_AST1700_DEV_SCU,
+ ASPEED_AST1700_DEV_GPIO,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
ASPEED_AST1700_DEV_SPI0_MEM,
@@ -31,6 +32,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
[ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
[ASPEED_AST1700_DEV_ADC] = 0x00C00000,
[ASPEED_AST1700_DEV_SCU] = 0x00C02000,
+ [ASPEED_AST1700_DEV_GPIO] = 0x00C0B000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
[ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
@@ -98,6 +100,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SCU],
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->scu), 0));
+ /* GPIO */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_GPIO],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0));
+
/* LTPI controller */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
return;
@@ -127,6 +137,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
object_initialize_child(obj, "ioexp-scu[*]", &s->scu,
TYPE_ASPEED_2700_SCU);
+ /* GPIO */
+ object_initialize_child(obj, "ioexp-gpio[*]", &s->gpio,
+ "aspeed.gpio-ast2700");
+
/* LTPI controller */
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 6b9ad328dc..d998326536 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -1124,6 +1124,10 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].adc), 0,
aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ADC));
+ /* GPIO */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].gpio), 0,
+ aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO));
+
}
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700 model
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (12 preceding siblings ...)
2025-12-24 1:41 ` [PATCH v4 13/19] hw/arm/aspeed: Attach GPIO " Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-24 11:04 ` Cédric Le Goater
2026-01-07 14:53 ` Cédric Le Goater
2025-12-24 1:41 ` [PATCH v4 15/19] hw/arm/aspeed: Attach WDT " Kane Chen via
` (6 subsequent siblings)
20 siblings, 2 replies; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the I2C controller to the AST1700 model by mapping its MMIO
region and wiring its interrupt line.
This patch also adds a bus_label property to distinguish I2C buses on
the BMC from those on external boards. This prevents user-specified
I2C devices from being attached to the wrong bus when provided via CLI.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/arm/aspeed_ast1700.h | 2 ++
include/hw/arm/aspeed_soc.h | 2 ++
include/hw/i2c/aspeed_i2c.h | 1 +
hw/arm/aspeed_ast1700.c | 18 ++++++++++++
hw/arm/aspeed_ast27x0.c | 51 +++++++++++++++++++++++++++++++--
hw/i2c/aspeed_i2c.c | 19 ++++++++++--
6 files changed, 88 insertions(+), 5 deletions(-)
diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
index 7ea6ff4c1a..d4b7abee7d 100644
--- a/include/hw/arm/aspeed_ast1700.h
+++ b/include/hw/arm/aspeed_ast1700.h
@@ -12,6 +12,7 @@
#include "hw/misc/aspeed_scu.h"
#include "hw/adc/aspeed_adc.h"
#include "hw/gpio/aspeed_gpio.h"
+#include "hw/i2c/aspeed_i2c.h"
#include "hw/misc/aspeed_ltpi.h"
#include "hw/ssi/aspeed_smc.h"
#include "hw/char/serial-mm.h"
@@ -34,6 +35,7 @@ struct AspeedAST1700SoCState {
AspeedADCState adc;
AspeedSCUState scu;
AspeedGPIOState gpio;
+ AspeedI2CState i2c;
};
#endif /* ASPEED_AST1700_H */
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index b051d0eb3a..4ea2521041 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -290,6 +290,8 @@ enum {
ASPEED_DEV_LTPI_CTRL2,
ASPEED_DEV_LTPI_IO0,
ASPEED_DEV_LTPI_IO1,
+ ASPEED_DEV_IOEXP0_I2C,
+ ASPEED_DEV_IOEXP1_I2C,
ASPEED_DEV_IOEXP0_INTCIO,
ASPEED_DEV_IOEXP1_INTCIO,
};
diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
index 2daacc10ce..babbad5ed9 100644
--- a/include/hw/i2c/aspeed_i2c.h
+++ b/include/hw/i2c/aspeed_i2c.h
@@ -269,6 +269,7 @@ struct AspeedI2CState {
uint32_t intr_status;
uint32_t ctrl_global;
uint32_t new_clk_divider;
+ char *bus_label;
MemoryRegion pool_iomem;
uint8_t share_pool[ASPEED_I2C_SHARE_POOL_SIZE];
diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
index 9a6019908e..fad3b86e8d 100644
--- a/hw/arm/aspeed_ast1700.c
+++ b/hw/arm/aspeed_ast1700.c
@@ -22,6 +22,7 @@ enum {
ASPEED_AST1700_DEV_ADC,
ASPEED_AST1700_DEV_SCU,
ASPEED_AST1700_DEV_GPIO,
+ ASPEED_AST1700_DEV_I2C,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
ASPEED_AST1700_DEV_SPI0_MEM,
@@ -33,6 +34,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
[ASPEED_AST1700_DEV_ADC] = 0x00C00000,
[ASPEED_AST1700_DEV_SCU] = 0x00C02000,
[ASPEED_AST1700_DEV_GPIO] = 0x00C0B000,
+ [ASPEED_AST1700_DEV_I2C] = 0x00C0F000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
[ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
@@ -108,6 +110,18 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_GPIO],
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0));
+ /* I2C */
+ snprintf(dev_name, sizeof(dev_name), "ioexp%d", s->board_idx);
+ qdev_prop_set_string(DEVICE(&s->i2c), "bus-label", dev_name);
+ object_property_set_link(OBJECT(&s->i2c), "dram",
+ OBJECT(&s->iomem), errp);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I2C],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c), 0));
+
/* LTPI controller */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
return;
@@ -141,6 +155,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
object_initialize_child(obj, "ioexp-gpio[*]", &s->gpio,
"aspeed.gpio-ast2700");
+ /* I2C */
+ object_initialize_child(obj, "ioexp-i2c[*]", &s->i2c,
+ "aspeed.i2c-ast2700");
+
/* LTPI controller */
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index d998326536..ca3adf9a50 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -205,6 +205,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] = {
[ASPEED_DEV_ETH3] = 196,
[ASPEED_DEV_PECI] = 197,
[ASPEED_DEV_SDHCI] = 197,
+ [ASPEED_DEV_IOEXP0_I2C] = 198,
+ [ASPEED_DEV_IOEXP1_I2C] = 200,
};
/* GICINT 128 */
@@ -267,6 +269,18 @@ static const int ast2700_gic133_gic197_intcmap[] = {
[ASPEED_DEV_PECI] = 4,
};
+/* Primary AST1700 Interrupts */
+/* A1: GICINT 198 */
+static const int ast2700_gic198_intcmap[] = {
+ [ASPEED_DEV_IOEXP0_I2C] = 0, /* 0 - 15 */
+};
+
+/* Secondary AST1700 Interrupts */
+/* A1: GINTC 200 */
+static const int ast2700_gic200_intcmap[] = {
+ [ASPEED_DEV_IOEXP1_I2C] = 0, /* 0 - 15 */
+};
+
/* GICINT 128 ~ 136 */
/* GICINT 192 ~ 201 */
struct gic_intc_irq_info {
@@ -283,9 +297,9 @@ static const struct gic_intc_irq_info ast2700_gic_intcmap[] = {
{195, 1, 3, ast2700_gic131_gic195_intcmap},
{196, 1, 4, ast2700_gic132_gic196_intcmap},
{197, 1, 5, ast2700_gic133_gic197_intcmap},
- {198, 1, 6, NULL},
+ {198, 2, 0, ast2700_gic198_intcmap},
{199, 1, 7, NULL},
- {200, 1, 8, NULL},
+ {200, 3, 0, ast2700_gic200_intcmap},
{201, 1, 9, NULL},
{128, 0, 1, ast2700_gic128_gic192_intcmap},
{129, 0, 2, NULL},
@@ -327,14 +341,23 @@ static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev,
int or_idx;
int idx;
int i;
+ OrIRQState *porgates;
for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
assert(ast2700_gic_intcmap[i].ptr);
or_idx = ast2700_gic_intcmap[i].orgate_idx;
idx = ast2700_gic_intcmap[i].intc_idx;
- return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
+ if (idx < ASPEED_INTC_NUM) {
+ porgates = &a->intc[idx].orgates[or_idx];
+ return qdev_get_gpio_in(DEVICE(porgates),
+ ast2700_gic_intcmap[i].ptr[dev] + index);
+ } else {
+ idx -= ASPEED_INTC_NUM;
+ porgates = &a->intcioexp[idx].orgates[or_idx];
+ return qdev_get_gpio_in(DEVICE(porgates),
ast2700_gic_intcmap[i].ptr[dev] + index);
+ }
}
}
@@ -1098,6 +1121,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
/* IO Expander */
for (i = 0; i < sc->ioexp_num; i++) {
+ AspeedI2CClass *i2c_ctl;
+
qdev_prop_set_uint8(DEVICE(&s->ioexp[i]), "board-idx", i);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) {
return;
@@ -1128,6 +1153,26 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].gpio), 0,
aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO));
+ /* I2C */
+ i2c_ctl = ASPEED_I2C_GET_CLASS(&s->ioexp[i].i2c);
+ for (int j = 0; j < i2c_ctl->num_busses; j++) {
+ /*
+ * For I2C on AST1700:
+ * I2C bus interrupts are connected to the OR gate from bit 0 to bit
+ * 15, and the OR gate output pin is connected to the input pin of
+ * GICINT192 of IO expander Interrupt controller (INTC2/3). Then,
+ * the output pin is connected to the INTC (CPU Die) input pin, and
+ * its output pin is connected to the GIC.
+ *
+ * I2C bus 0 is connected to the OR gate at bit 0.
+ * I2C bus 15 is connected to the OR gate at bit 15.
+ */
+ irq = aspeed_soc_ast2700_get_irq_index(s,
+ ASPEED_DEV_IOEXP0_I2C + i,
+ j);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].i2c.busses[j]),
+ 0, irq);
+ }
}
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 83fb906bdc..ca84068bb4 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -1261,6 +1261,7 @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
static const Property aspeed_i2c_properties[] = {
DEFINE_PROP_LINK("dram", AspeedI2CState, dram_mr,
TYPE_MEMORY_REGION, MemoryRegion *),
+ DEFINE_PROP_STRING("bus-label", AspeedI2CState, bus_label),
};
static void aspeed_i2c_class_init(ObjectClass *klass, const void *data)
@@ -1421,14 +1422,28 @@ static void aspeed_i2c_bus_realize(DeviceState *dev, Error **errp)
{
AspeedI2CBus *s = ASPEED_I2C_BUS(dev);
AspeedI2CClass *aic;
- g_autofree char *name = g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s->id);
- g_autofree char *pool_name = g_strdup_printf("%s.pool", name);
+ g_autofree char *name = NULL;
+ g_autofree char *pool_name = NULL;
if (!s->controller) {
error_setg(errp, TYPE_ASPEED_I2C_BUS ": 'controller' link not set");
return;
}
+ /*
+ * I2C bus naming:
+ * - Empty bus_label -> BMC internal controller, use default name.
+ * - Non-empty bus_label -> external/addon controller, prefix with label
+ * to avoid conflicts and show bus origin.
+ */
+ if (!s->controller->bus_label || (strlen(s->controller->bus_label) == 0)) {
+ name = g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s->id);
+ } else {
+ name = g_strdup_printf("aspeed.%s.i2c.bus.%d",
+ s->controller->bus_label, s->id);
+ }
+ pool_name = g_strdup_printf("%s.pool", name);
+
aic = ASPEED_I2C_GET_CLASS(s->controller);
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 15/19] hw/arm/aspeed: Attach WDT device to AST1700 model
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (13 preceding siblings ...)
2025-12-24 1:41 ` [PATCH v4 14/19] hw/arm/aspeed: attach I2C " Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 16/19] hw/arm/aspeed: Attach PWM " Kane Chen via
` (5 subsequent siblings)
20 siblings, 1 reply; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS, Cédric Le Goater
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the WDT device to AST1700 model.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_ast1700.h | 4 ++++
hw/arm/aspeed_ast1700.c | 24 ++++++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
index d4b7abee7d..f43c0c5475 100644
--- a/include/hw/arm/aspeed_ast1700.h
+++ b/include/hw/arm/aspeed_ast1700.h
@@ -15,8 +15,11 @@
#include "hw/i2c/aspeed_i2c.h"
#include "hw/misc/aspeed_ltpi.h"
#include "hw/ssi/aspeed_smc.h"
+#include "hw/watchdog/wdt_aspeed.h"
#include "hw/char/serial-mm.h"
+#define AST1700_WDT_NUM 9
+
#define TYPE_ASPEED_AST1700 "aspeed.ast1700"
OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700)
@@ -36,6 +39,7 @@ struct AspeedAST1700SoCState {
AspeedSCUState scu;
AspeedGPIOState gpio;
AspeedI2CState i2c;
+ AspeedWDTState wdt[AST1700_WDT_NUM];
};
#endif /* ASPEED_AST1700_H */
diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
index fad3b86e8d..9fb84dd159 100644
--- a/hw/arm/aspeed_ast1700.c
+++ b/hw/arm/aspeed_ast1700.c
@@ -25,6 +25,7 @@ enum {
ASPEED_AST1700_DEV_I2C,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
+ ASPEED_AST1700_DEV_WDT,
ASPEED_AST1700_DEV_SPI0_MEM,
};
@@ -37,6 +38,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
[ASPEED_AST1700_DEV_I2C] = 0x00C0F000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
+ [ASPEED_AST1700_DEV_WDT] = 0x00C37000,
[ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
};
@@ -129,6 +131,22 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->iomem,
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_CTRL],
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0));
+ /* WDT */
+ for (int i = 0; i < AST1700_WDT_NUM; i++) {
+ AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
+ hwaddr wdt_offset = aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_WDT] +
+ i * awc->iosize;
+
+ object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
+ errp);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ wdt_offset,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->wdt[i]), 0));
+ }
+
}
static void aspeed_ast1700_instance_init(Object *obj)
@@ -163,6 +181,12 @@ static void aspeed_ast1700_instance_init(Object *obj)
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
+ /* WDT */
+ for (int i = 0; i < AST1700_WDT_NUM; i++) {
+ object_initialize_child(obj, "ioexp-wdt[*]",
+ &s->wdt[i], "aspeed.wdt-ast2700");
+ }
+
return;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 16/19] hw/arm/aspeed: Attach PWM device to AST1700 model
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (14 preceding siblings ...)
2025-12-24 1:41 ` [PATCH v4 15/19] hw/arm/aspeed: Attach WDT " Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 17/19] hw/arm/aspeed: Attach SGPIOM " Kane Chen via
` (4 subsequent siblings)
20 siblings, 1 reply; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS, Cédric Le Goater
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the PWM device to AST1700 model.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_ast1700.h | 2 ++
hw/arm/aspeed_ast1700.c | 13 +++++++++++++
2 files changed, 15 insertions(+)
diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
index f43c0c5475..7292719dc2 100644
--- a/include/hw/arm/aspeed_ast1700.h
+++ b/include/hw/arm/aspeed_ast1700.h
@@ -14,6 +14,7 @@
#include "hw/gpio/aspeed_gpio.h"
#include "hw/i2c/aspeed_i2c.h"
#include "hw/misc/aspeed_ltpi.h"
+#include "hw/misc/aspeed_pwm.h"
#include "hw/ssi/aspeed_smc.h"
#include "hw/watchdog/wdt_aspeed.h"
#include "hw/char/serial-mm.h"
@@ -39,6 +40,7 @@ struct AspeedAST1700SoCState {
AspeedSCUState scu;
AspeedGPIOState gpio;
AspeedI2CState i2c;
+ AspeedPWMState pwm;
AspeedWDTState wdt[AST1700_WDT_NUM];
};
diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
index 9fb84dd159..5a2552aa25 100644
--- a/hw/arm/aspeed_ast1700.c
+++ b/hw/arm/aspeed_ast1700.c
@@ -18,6 +18,7 @@
enum {
ASPEED_AST1700_DEV_SPI0,
+ ASPEED_AST1700_DEV_PWM,
ASPEED_AST1700_DEV_SRAM,
ASPEED_AST1700_DEV_ADC,
ASPEED_AST1700_DEV_SCU,
@@ -31,6 +32,7 @@ enum {
static const hwaddr aspeed_ast1700_io_memmap[] = {
[ASPEED_AST1700_DEV_SPI0] = 0x00030000,
+ [ASPEED_AST1700_DEV_PWM] = 0x000C0000,
[ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
[ASPEED_AST1700_DEV_ADC] = 0x00C00000,
[ASPEED_AST1700_DEV_SCU] = 0x00C02000,
@@ -124,6 +126,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I2C],
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c), 0));
+ /* PWM */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_PWM],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pwm), 0));
+
/* LTPI controller */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
return;
@@ -177,6 +187,9 @@ static void aspeed_ast1700_instance_init(Object *obj)
object_initialize_child(obj, "ioexp-i2c[*]", &s->i2c,
"aspeed.i2c-ast2700");
+ /* PWM */
+ object_initialize_child(obj, "pwm", &s->pwm, TYPE_ASPEED_PWM);
+
/* LTPI controller */
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 17/19] hw/arm/aspeed: Attach SGPIOM device to AST1700 model
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (15 preceding siblings ...)
2025-12-24 1:41 ` [PATCH v4 16/19] hw/arm/aspeed: Attach PWM " Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 18/19] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device Kane Chen via
` (3 subsequent siblings)
20 siblings, 1 reply; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS, Cédric Le Goater
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Connect the SGPIOM device to AST1700 model.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_ast1700.h | 3 +++
hw/arm/aspeed_ast1700.c | 21 +++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
index 7292719dc2..490f2a3b05 100644
--- a/include/hw/arm/aspeed_ast1700.h
+++ b/include/hw/arm/aspeed_ast1700.h
@@ -12,6 +12,7 @@
#include "hw/misc/aspeed_scu.h"
#include "hw/adc/aspeed_adc.h"
#include "hw/gpio/aspeed_gpio.h"
+#include "hw/gpio/aspeed_sgpio.h"
#include "hw/i2c/aspeed_i2c.h"
#include "hw/misc/aspeed_ltpi.h"
#include "hw/misc/aspeed_pwm.h"
@@ -19,6 +20,7 @@
#include "hw/watchdog/wdt_aspeed.h"
#include "hw/char/serial-mm.h"
+#define AST1700_SGPIO_NUM 2
#define AST1700_WDT_NUM 9
#define TYPE_ASPEED_AST1700 "aspeed.ast1700"
@@ -39,6 +41,7 @@ struct AspeedAST1700SoCState {
AspeedADCState adc;
AspeedSCUState scu;
AspeedGPIOState gpio;
+ AspeedSGPIOState sgpiom[AST1700_SGPIO_NUM];
AspeedI2CState i2c;
AspeedPWMState pwm;
AspeedWDTState wdt[AST1700_WDT_NUM];
diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
index 5a2552aa25..ca0ce4e2c2 100644
--- a/hw/arm/aspeed_ast1700.c
+++ b/hw/arm/aspeed_ast1700.c
@@ -23,6 +23,8 @@ enum {
ASPEED_AST1700_DEV_ADC,
ASPEED_AST1700_DEV_SCU,
ASPEED_AST1700_DEV_GPIO,
+ ASPEED_AST1700_DEV_SGPIOM0,
+ ASPEED_AST1700_DEV_SGPIOM1,
ASPEED_AST1700_DEV_I2C,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
@@ -37,6 +39,8 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
[ASPEED_AST1700_DEV_ADC] = 0x00C00000,
[ASPEED_AST1700_DEV_SCU] = 0x00C02000,
[ASPEED_AST1700_DEV_GPIO] = 0x00C0B000,
+ [ASPEED_AST1700_DEV_SGPIOM0] = 0x00C0C000,
+ [ASPEED_AST1700_DEV_SGPIOM1] = 0x00C0D000,
[ASPEED_AST1700_DEV_I2C] = 0x00C0F000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
@@ -141,6 +145,17 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->iomem,
aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_CTRL],
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0));
+
+ /* SGPIOM */
+ for (int i = 0; i < AST1700_SGPIO_NUM; i++) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sgpiom[i]), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SGPIOM0 + i],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sgpiom[i]), 0));
+ }
+
/* WDT */
for (int i = 0; i < AST1700_WDT_NUM; i++) {
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
@@ -194,6 +209,12 @@ static void aspeed_ast1700_instance_init(Object *obj)
object_initialize_child(obj, "ltpi-ctrl",
&s->ltpi, TYPE_ASPEED_LTPI);
+ /* SGPIOM */
+ for (int i = 0; i < AST1700_SGPIO_NUM; i++) {
+ object_initialize_child(obj, "ioexp-sgpiom[*]", &s->sgpiom[i],
+ "aspeed.sgpio-ast2700");
+ }
+
/* WDT */
for (int i = 0; i < AST1700_WDT_NUM; i++) {
object_initialize_child(obj, "ioexp-wdt[*]",
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 18/19] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (16 preceding siblings ...)
2025-12-24 1:41 ` [PATCH v4 17/19] hw/arm/aspeed: Attach SGPIOM " Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-24 10:43 ` Cédric Le Goater
2025-12-24 1:41 ` [PATCH v4 19/19] hw/arm/aspeed: Enable AST1700 IO expander support Kane Chen via
` (2 subsequent siblings)
20 siblings, 1 reply; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
AST1700 exposes more I3C buses than the current dummy I3C model
provides. When Linux probes the I3C devices on AST1700 this mismatch
can trigger a kernel panic. Model the I3C block as an unimplemented
device to make the missing functionality explicit and avoid unexpected
side effects.
This wires up the I3C interrupt lines for the IO expanders and adds the
corresponding device entries for the AST1700 model.
No functional I3C emulation is provided yet; this only prevents crashes and
documents the missing piece.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
include/hw/arm/aspeed_ast1700.h | 3 +++
include/hw/arm/aspeed_soc.h | 2 ++
hw/arm/aspeed_ast1700.c | 15 +++++++++++++++
hw/arm/aspeed_ast27x0.c | 18 ++++++++++++++++--
4 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
index 490f2a3b05..874b4d63fe 100644
--- a/include/hw/arm/aspeed_ast1700.h
+++ b/include/hw/arm/aspeed_ast1700.h
@@ -19,6 +19,7 @@
#include "hw/ssi/aspeed_smc.h"
#include "hw/watchdog/wdt_aspeed.h"
#include "hw/char/serial-mm.h"
+#include "hw/misc/unimp.h"
#define AST1700_SGPIO_NUM 2
#define AST1700_WDT_NUM 9
@@ -45,6 +46,8 @@ struct AspeedAST1700SoCState {
AspeedI2CState i2c;
AspeedPWMState pwm;
AspeedWDTState wdt[AST1700_WDT_NUM];
+
+ UnimplementedDeviceState i3c;
};
#endif /* ASPEED_AST1700_H */
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 4ea2521041..b185b04186 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -294,6 +294,8 @@ enum {
ASPEED_DEV_IOEXP1_I2C,
ASPEED_DEV_IOEXP0_INTCIO,
ASPEED_DEV_IOEXP1_INTCIO,
+ ASPEED_DEV_IOEXP0_I3C,
+ ASPEED_DEV_IOEXP1_I3C,
};
const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
index ca0ce4e2c2..5f3c56e6cc 100644
--- a/hw/arm/aspeed_ast1700.c
+++ b/hw/arm/aspeed_ast1700.c
@@ -15,6 +15,7 @@
#define AST2700_SOC_LTPI_SIZE 0x01000000
#define AST1700_SOC_SRAM_SIZE 0x00040000
+#define AST1700_SOC_I3C_SIZE 0x00010000
enum {
ASPEED_AST1700_DEV_SPI0,
@@ -26,6 +27,7 @@ enum {
ASPEED_AST1700_DEV_SGPIOM0,
ASPEED_AST1700_DEV_SGPIOM1,
ASPEED_AST1700_DEV_I2C,
+ ASPEED_AST1700_DEV_I3C,
ASPEED_AST1700_DEV_UART12,
ASPEED_AST1700_DEV_LTPI_CTRL,
ASPEED_AST1700_DEV_WDT,
@@ -42,6 +44,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
[ASPEED_AST1700_DEV_SGPIOM0] = 0x00C0C000,
[ASPEED_AST1700_DEV_SGPIOM1] = 0x00C0D000,
[ASPEED_AST1700_DEV_I2C] = 0x00C0F000,
+ [ASPEED_AST1700_DEV_I3C] = 0x00C20000,
[ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
[ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
[ASPEED_AST1700_DEV_WDT] = 0x00C37000,
@@ -172,6 +175,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->wdt[i]), 0));
}
+ /* I3C */
+ qdev_prop_set_string(DEVICE(&s->i3c), "name", "ioexp-i3c");
+ qdev_prop_set_uint64(DEVICE(&s->i3c), "size", AST1700_SOC_I3C_SIZE);
+ sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp);
+ memory_region_add_subregion_overlap(&s->iomem,
+ aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I3C],
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i3c), 0),
+ -1000);
}
static void aspeed_ast1700_instance_init(Object *obj)
@@ -221,6 +232,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
&s->wdt[i], "aspeed.wdt-ast2700");
}
+ /* I3C */
+ object_initialize_child(obj, "ioexp-i3c[*]", &s->i3c,
+ TYPE_UNIMPLEMENTED_DEVICE);
+
return;
}
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index ca3adf9a50..0807481162 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -206,7 +206,9 @@ static const int aspeed_soc_ast2700a1_irqmap[] = {
[ASPEED_DEV_PECI] = 197,
[ASPEED_DEV_SDHCI] = 197,
[ASPEED_DEV_IOEXP0_I2C] = 198,
+ [ASPEED_DEV_IOEXP0_I3C] = 199,
[ASPEED_DEV_IOEXP1_I2C] = 200,
+ [ASPEED_DEV_IOEXP1_I3C] = 201,
};
/* GICINT 128 */
@@ -275,12 +277,24 @@ static const int ast2700_gic198_intcmap[] = {
[ASPEED_DEV_IOEXP0_I2C] = 0, /* 0 - 15 */
};
+/* Primary AST1700 Interrupts */
+/* A1: GINTC 199 */
+static const int ast2700_gic199_intcmap[] = {
+ [ASPEED_DEV_IOEXP0_I3C] = 0, /* 0 - 15 */
+};
+
/* Secondary AST1700 Interrupts */
/* A1: GINTC 200 */
static const int ast2700_gic200_intcmap[] = {
[ASPEED_DEV_IOEXP1_I2C] = 0, /* 0 - 15 */
};
+/* Secondary AST1700 Interrupts */
+/* A1: GINTC 201 */
+static const int ast2700_gic201_intcmap[] = {
+ [ASPEED_DEV_IOEXP1_I3C] = 0, /* 0 - 15 */
+};
+
/* GICINT 128 ~ 136 */
/* GICINT 192 ~ 201 */
struct gic_intc_irq_info {
@@ -298,9 +312,9 @@ static const struct gic_intc_irq_info ast2700_gic_intcmap[] = {
{196, 1, 4, ast2700_gic132_gic196_intcmap},
{197, 1, 5, ast2700_gic133_gic197_intcmap},
{198, 2, 0, ast2700_gic198_intcmap},
- {199, 1, 7, NULL},
+ {199, 2, 1, ast2700_gic199_intcmap},
{200, 3, 0, ast2700_gic200_intcmap},
- {201, 1, 9, NULL},
+ {201, 3, 1, ast2700_gic201_intcmap},
{128, 0, 1, ast2700_gic128_gic192_intcmap},
{129, 0, 2, NULL},
{130, 0, 3, ast2700_gic130_gic194_intcmap},
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [PATCH v4 19/19] hw/arm/aspeed: Enable AST1700 IO expander support
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (17 preceding siblings ...)
2025-12-24 1:41 ` [PATCH v4 18/19] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device Kane Chen via
@ 2025-12-24 1:41 ` Kane Chen via
2025-12-24 10:43 ` Cédric Le Goater
2025-12-29 19:37 ` [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Nabih Estefan
2026-01-19 7:45 ` Cédric Le Goater
20 siblings, 1 reply; 74+ messages in thread
From: Kane Chen via @ 2025-12-24 1:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan, Kane-Chen-AS
From: Kane-Chen-AS <kane_chen@aspeedtech.com>
Set ioexp_num to 2 to enable AST1700 IO expander support.
Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 0807481162..2eb857b8e0 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -1260,7 +1260,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
sc->macs_num = 3;
sc->uarts_num = 13;
sc->num_cpus = 4;
- sc->ioexp_num = 0;
+ sc->ioexp_num = 2;
sc->uarts_base = ASPEED_DEV_UART0;
sc->irqmap = aspeed_soc_ast2700a1_irqmap;
sc->memmap = aspeed_soc_ast2700_memmap;
--
2.43.0
^ permalink raw reply related [flat|nested] 74+ messages in thread
* Re: [PATCH v4 01/19] hw/misc: Add LTPI controller
2025-12-24 1:41 ` [PATCH v4 01/19] hw/misc: Add LTPI controller Kane Chen via
@ 2025-12-24 10:36 ` Cédric Le Goater
2025-12-29 19:37 ` Nabih Estefan
0 siblings, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2025-12-24 10:36 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan
On 12/24/25 02:41, Kane Chen via wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP DC-SCM
> 2.0 specification:
> https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
>
> LTPI is a protocol and physical interface for tunneling various low-speed
> signals between the HPM and SCM. As shown in Figure 2, the AST27x0 (left)
> integrates two LTPI controllers, allowing it to connect to up to two
> extended boards.
>
> This commit introduces a simple device model for the ASPEED LTPI
> controller in QEMU.
>
> The model includes basic MMIO read/write operations and sets default
> register values during reset to emulate a link-up state.
>
> Implements register space with read/write callbacks.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
> ---
> include/hw/misc/aspeed_ltpi.h | 33 ++++++
> hw/misc/aspeed_ltpi.c | 193 ++++++++++++++++++++++++++++++++++
> hw/misc/meson.build | 1 +
> 3 files changed, 227 insertions(+)
> create mode 100644 include/hw/misc/aspeed_ltpi.h
> create mode 100644 hw/misc/aspeed_ltpi.c
>
> diff --git a/include/hw/misc/aspeed_ltpi.h b/include/hw/misc/aspeed_ltpi.h
> new file mode 100644
> index 0000000000..e991afc666
> --- /dev/null
> +++ b/include/hw/misc/aspeed_ltpi.h
> @@ -0,0 +1,33 @@
> +/*
> + * ASPEED LTPI Controller
> + *
> + * Copyright (C) 2025 ASPEED Technology Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +#ifndef ASPEED_LTPI_H
> +#define ASPEED_LTPI_H
> +
> +#include "hw/sysbus.h"
> +
> +#define TYPE_ASPEED_LTPI "aspeed.ltpi-ctrl"
> +OBJECT_DECLARE_SIMPLE_TYPE(AspeedLTPIState, ASPEED_LTPI)
> +
> +#define ASPEED_LTPI_TOTAL_SIZE 0x900
> +#define ASPEED_LTPI_CTRL_SIZE 0x200
> +#define ASPEED_LTPI_PHY_SIZE 0x100
> +#define ASPEED_LTPI_TOP_SIZE 0x100
> +
> +struct AspeedLTPIState {
> + SysBusDevice parent;
> + MemoryRegion mmio;
> + MemoryRegion mmio_ctrl;
> + MemoryRegion mmio_phy;
> + MemoryRegion mmio_top;
> +
> + uint32_t ctrl_regs[ASPEED_LTPI_CTRL_SIZE >> 2];
> + uint32_t phy_regs[ASPEED_LTPI_PHY_SIZE >> 2];
> + uint32_t top_regs[ASPEED_LTPI_TOP_SIZE >> 2];
> +};
> +
> +#endif /* ASPEED_LTPI_H */
> diff --git a/hw/misc/aspeed_ltpi.c b/hw/misc/aspeed_ltpi.c
> new file mode 100644
> index 0000000000..131cea9c6b
> --- /dev/null
> +++ b/hw/misc/aspeed_ltpi.c
> @@ -0,0 +1,193 @@
> +/*
> + * ASPEED LTPI Controller
> + *
> + * Copyright (C) 2025 ASPEED Technology Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "migration/vmstate.h"
> +#include "hw/misc/aspeed_ltpi.h"
> +
> +#define ASPEED_LTPI_CTRL_BASE 0x000
> +#define ASPEED_LTPI_PHY_BASE 0x200
> +#define ASPEED_LTPI_TOP_BASE 0x800
> +
> +#define LTPI_CTRL_LINK_MNG 0x42
> +#define LTPI_PHY_MODE 0x0
> +
> +static uint64_t aspeed_ltpi_top_read(void *opaque, hwaddr offset, unsigned size)
> +{
> + AspeedLTPIState *s = opaque;
> + uint32_t idx = offset >> 2;
> +
> + return s->top_regs[idx];
> +}
> +
> +static void aspeed_ltpi_top_write(void *opaque, hwaddr offset,
> + uint64_t val, unsigned size)
> +{
> + AspeedLTPIState *s = opaque;
> + uint32_t idx = offset >> 2;
> +
> + switch (offset) {
> + default:
> + s->top_regs[idx] = (uint32_t)val;
> + break;
> + }
> +}
> +
> +static const MemoryRegionOps aspeed_ltpi_top_ops = {
> + .read = aspeed_ltpi_top_read,
> + .write = aspeed_ltpi_top_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 4,
> + },
> +};
> +
> +static uint64_t aspeed_ltpi_phy_read(void *opaque, hwaddr offset, unsigned size)
> +{
> + AspeedLTPIState *s = opaque;
> + uint32_t idx = offset >> 2;
> +
> + return s->phy_regs[idx];
> +}
> +
> +static void aspeed_ltpi_phy_write(void *opaque, hwaddr offset,
> + uint64_t val, unsigned size)
> +{
> + AspeedLTPIState *s = opaque;
> + uint32_t idx = offset >> 2;
> +
> + switch (offset) {
> + default:
> + s->phy_regs[idx] = (uint32_t)val;
> + break;
> + }
> +}
> +
> +static const MemoryRegionOps aspeed_ltpi_phy_ops = {
> + .read = aspeed_ltpi_phy_read,
> + .write = aspeed_ltpi_phy_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 4,
> + },
> +};
> +
> +static uint64_t aspeed_ltpi_ctrl_read(void *opaque,
> + hwaddr offset, unsigned size)
> +{
> + AspeedLTPIState *s = opaque;
> + uint32_t idx = offset >> 2;
> +
> + return s->ctrl_regs[idx];
> +}
> +
> +static void aspeed_ltpi_ctrl_write(void *opaque, hwaddr offset,
> + uint64_t val, unsigned size)
> +{
> + AspeedLTPIState *s = opaque;
> + uint32_t idx = offset >> 2;
> +
> + switch (offset) {
> + default:
> + s->ctrl_regs[idx] = (uint32_t)val;
> + break;
> + }
> +}
> +
> +static const MemoryRegionOps aspeed_ltpi_ctrl_ops = {
> + .read = aspeed_ltpi_ctrl_read,
> + .write = aspeed_ltpi_ctrl_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 4,
> + },
> +};
> +
> +static void aspeed_ltpi_reset(DeviceState *dev)
> +{
> + AspeedLTPIState *s = ASPEED_LTPI(dev);
> +
> + memset(s->ctrl_regs, 0, sizeof(s->ctrl_regs));
> + memset(s->phy_regs, 0, sizeof(s->phy_regs));
> + memset(s->top_regs, 0, sizeof(s->top_regs));
> + /* set default values */
> + s->ctrl_regs[LTPI_CTRL_LINK_MNG] = 0x11900007;
> + s->phy_regs[LTPI_PHY_MODE] = 0x2;
> +}
> +
> +
> +static const VMStateDescription vmstate_aspeed_ltpi = {
> + .name = TYPE_ASPEED_LTPI,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32_ARRAY(ctrl_regs, AspeedLTPIState,
> + ASPEED_LTPI_CTRL_SIZE >> 2),
> + VMSTATE_UINT32_ARRAY(phy_regs, AspeedLTPIState,
> + ASPEED_LTPI_PHY_SIZE >> 2),
> + VMSTATE_UINT32_ARRAY(top_regs, AspeedLTPIState,
> + ASPEED_LTPI_TOP_SIZE >> 2),
> +
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void aspeed_ltpi_realize(DeviceState *dev, Error **errp)
> +{
> + AspeedLTPIState *s = ASPEED_LTPI(dev);
> +
> + memory_region_init(&s->mmio, OBJECT(s), TYPE_ASPEED_LTPI,
> + ASPEED_LTPI_TOTAL_SIZE);
> +
> + memory_region_init_io(&s->mmio_ctrl, OBJECT(s),
> + &aspeed_ltpi_ctrl_ops, s,
> + "aspeed-ltpi-ctrl", ASPEED_LTPI_CTRL_SIZE);
> +
> + memory_region_init_io(&s->mmio_phy, OBJECT(s),
> + &aspeed_ltpi_phy_ops, s,
> + "aspeed-ltpi-phy", ASPEED_LTPI_PHY_SIZE);
> +
> + memory_region_init_io(&s->mmio_top, OBJECT(s),
> + &aspeed_ltpi_top_ops, s,
> + "aspeed-ltpi-top", ASPEED_LTPI_TOP_SIZE);
> +
> + memory_region_add_subregion(&s->mmio,
> + ASPEED_LTPI_CTRL_BASE, &s->mmio_ctrl);
> + memory_region_add_subregion(&s->mmio,
> + ASPEED_LTPI_PHY_BASE, &s->mmio_phy);
> + memory_region_add_subregion(&s->mmio,
> + ASPEED_LTPI_TOP_BASE, &s->mmio_top);
> +
> + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
> +}
> +
> +static void aspeed_ltpi_class_init(ObjectClass *klass, const void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + dc->realize = aspeed_ltpi_realize;
> + dc->vmsd = &vmstate_aspeed_ltpi;
> + device_class_set_legacy_reset(dc, aspeed_ltpi_reset);
> +}
> +
> +static const TypeInfo aspeed_ltpi_info = {
> + .name = TYPE_ASPEED_LTPI,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(AspeedLTPIState),
> + .class_init = aspeed_ltpi_class_init,
> +};
> +
> +static void aspeed_ltpi_register_types(void)
> +{
> + type_register_static(&aspeed_ltpi_info);
> +}
> +
> +type_init(aspeed_ltpi_register_types);
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index b1d8d8e5d2..45b16e7797 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -136,6 +136,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> 'aspeed_hace.c',
> 'aspeed_i3c.c',
> 'aspeed_lpc.c',
> + 'aspeed_ltpi.c',
> 'aspeed_scu.c',
> 'aspeed_sbc.c',
> 'aspeed_sdmc.c',
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 03/19] hw/misc: Add basic Aspeed PWM model
2025-12-24 1:41 ` [PATCH v4 03/19] hw/misc: Add basic Aspeed PWM model Kane Chen via
@ 2025-12-24 10:37 ` Cédric Le Goater
2025-12-29 19:37 ` Nabih Estefan
0 siblings, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2025-12-24 10:37 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan
On 12/24/25 02:41, Kane Chen via wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
It should be From: clg ...
I will fix it. Don't resend for that.
Thanks,
C.
>
> Add an initial PWM model for Aspeed SoCs, including device state,
> register definitions, and basic initialization as a sysbus device.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> include/hw/arm/aspeed_soc.h | 3 +-
> include/hw/misc/aspeed_pwm.h | 31 +++++++++
> hw/misc/aspeed_pwm.c | 121 +++++++++++++++++++++++++++++++++++
> hw/misc/meson.build | 1 +
> hw/misc/trace-events | 4 ++
> 5 files changed, 159 insertions(+), 1 deletion(-)
> create mode 100644 include/hw/misc/aspeed_pwm.h
> create mode 100644 hw/misc/aspeed_pwm.c
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index bca10c387b..7b08cca908 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -28,6 +28,7 @@
> #include "hw/misc/aspeed_hace.h"
> #include "hw/misc/aspeed_sbc.h"
> #include "hw/misc/aspeed_sli.h"
> +#include "hw/misc/aspeed_pwm.h"
> #include "hw/watchdog/wdt_aspeed.h"
> #include "hw/net/ftgmac100.h"
> #include "target/arm/cpu.h"
> @@ -88,6 +89,7 @@ struct AspeedSoCState {
> MemoryRegion secsram;
> UnimplementedDeviceState sbc_unimplemented;
> AspeedSDMCState sdmc;
> + AspeedPWMState pwm;
> AspeedWDTState wdt[ASPEED_WDTS_NUM];
> FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
> AspeedMiiState mii[ASPEED_MACS_NUM];
> @@ -108,7 +110,6 @@ struct AspeedSoCState {
> UnimplementedDeviceState video;
> UnimplementedDeviceState emmc_boot_controller;
> UnimplementedDeviceState dpmcu;
> - UnimplementedDeviceState pwm;
> UnimplementedDeviceState espi;
> UnimplementedDeviceState udc;
> UnimplementedDeviceState ltpi;
> diff --git a/include/hw/misc/aspeed_pwm.h b/include/hw/misc/aspeed_pwm.h
> new file mode 100644
> index 0000000000..13dc3ea45b
> --- /dev/null
> +++ b/include/hw/misc/aspeed_pwm.h
> @@ -0,0 +1,31 @@
> +/*
> + * ASPEED PWM Controller
> + *
> + * Copyright (C) 2017-2021 IBM Corp.
> + *
> + * This code is licensed under the GPL version 2 or later. See
> + * the COPYING file in the top-level directory.
> + */
> +
> +#ifndef ASPEED_PWM_H
> +#define ASPEED_PWM_H
> +
> +#include "hw/sysbus.h"
> +
> +#define TYPE_ASPEED_PWM "aspeed.pwm"
> +#define ASPEED_PWM(obj) OBJECT_CHECK(AspeedPWMState, (obj), TYPE_ASPEED_PWM)
> +
> +#define ASPEED_PWM_NR_REGS (0x10C >> 2)
> +
> +typedef struct AspeedPWMState {
> + /* <private> */
> + SysBusDevice parent;
> +
> + /*< public >*/
> + MemoryRegion iomem;
> + qemu_irq irq;
> +
> + uint32_t regs[ASPEED_PWM_NR_REGS];
> +} AspeedPWMState;
> +
> +#endif /* _ASPEED_PWM_H_ */
> diff --git a/hw/misc/aspeed_pwm.c b/hw/misc/aspeed_pwm.c
> new file mode 100644
> index 0000000000..de209274af
> --- /dev/null
> +++ b/hw/misc/aspeed_pwm.c
> @@ -0,0 +1,121 @@
> +/*
> + * ASPEED PWM Controller
> + *
> + * Copyright (C) 2017-2021 IBM Corp.
> + *
> + * This code is licensed under the GPL version 2 or later. See
> + * the COPYING file in the top-level directory.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "qemu/error-report.h"
> +#include "hw/misc/aspeed_pwm.h"
> +#include "qapi/error.h"
> +#include "migration/vmstate.h"
> +
> +#include "trace.h"
> +
> +static uint64_t aspeed_pwm_read(void *opaque, hwaddr addr,
> + unsigned int size)
> +{
> + AspeedPWMState *s = ASPEED_PWM(opaque);
> + uint64_t val = 0;
> +
> + addr >>= 2;
> +
> + if (addr >= ASPEED_PWM_NR_REGS) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
> + __func__, addr << 2);
> + } else {
> + val = s->regs[addr];
> + }
> +
> + trace_aspeed_pwm_read(addr << 2, val);
> +
> + return val;
> +}
> +
> +static void aspeed_pwm_write(void *opaque, hwaddr addr, uint64_t data,
> + unsigned int size)
> +{
> + AspeedPWMState *s = ASPEED_PWM(opaque);
> +
> + trace_aspeed_pwm_write(addr, data);
> +
> + addr >>= 2;
> +
> + if (addr >= ASPEED_PWM_NR_REGS) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
> + __func__, addr << 2);
> + return;
> + }
> +
> + s->regs[addr] = data;
> +}
> +
> +static const MemoryRegionOps aspeed_pwm_ops = {
> + .read = aspeed_pwm_read,
> + .write = aspeed_pwm_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 4,
> + },
> +};
> +
> +static void aspeed_pwm_reset(DeviceState *dev)
> +{
> + struct AspeedPWMState *s = ASPEED_PWM(dev);
> +
> + memset(s->regs, 0, sizeof(s->regs));
> +}
> +
> +static void aspeed_pwm_realize(DeviceState *dev, Error **errp)
> +{
> + AspeedPWMState *s = ASPEED_PWM(dev);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> +
> + sysbus_init_irq(sbd, &s->irq);
> +
> + memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_pwm_ops, s,
> + TYPE_ASPEED_PWM, 0x1000);
> +
> + sysbus_init_mmio(sbd, &s->iomem);
> +}
> +
> +static const VMStateDescription vmstate_aspeed_pwm = {
> + .name = TYPE_ASPEED_PWM,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32_ARRAY(regs, AspeedPWMState, ASPEED_PWM_NR_REGS),
> + VMSTATE_END_OF_LIST(),
> + }
> +};
> +
> +static void aspeed_pwm_class_init(ObjectClass *klass, const void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->realize = aspeed_pwm_realize;
> + device_class_set_legacy_reset(dc, aspeed_pwm_reset);
> + dc->desc = "Aspeed PWM Controller";
> + dc->vmsd = &vmstate_aspeed_pwm;
> +}
> +
> +static const TypeInfo aspeed_pwm_info = {
> + .name = TYPE_ASPEED_PWM,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(AspeedPWMState),
> + .class_init = aspeed_pwm_class_init,
> +};
> +
> +static void aspeed_pwm_register_types(void)
> +{
> + type_register_static(&aspeed_pwm_info);
> +}
> +
> +type_init(aspeed_pwm_register_types);
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 45b16e7797..7afe1d0009 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -137,6 +137,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> 'aspeed_i3c.c',
> 'aspeed_lpc.c',
> 'aspeed_ltpi.c',
> + 'aspeed_pwm.c',
> 'aspeed_scu.c',
> 'aspeed_sbc.c',
> 'aspeed_sdmc.c',
> diff --git a/hw/misc/trace-events b/hw/misc/trace-events
> index eeb9243898..f7870babba 100644
> --- a/hw/misc/trace-events
> +++ b/hw/misc/trace-events
> @@ -299,6 +299,10 @@ aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64
> aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64
> aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
>
> +# aspeed_pwm.c
> +aspeed_pwm_read(uint64_t offset, uint64_t data) "read: offset 0x%" PRIx64 " data 0x%" PRIx64
> +aspeed_pwm_write(uint64_t offset, uint64_t data) "write: offset 0x%" PRIx64 " data 0x%" PRIx64
> +
> # aspeed_sdmc.c
> aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
> aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 04/19] hw/arm/aspeed: Add AST1700 LTPI expander device model
2025-12-24 1:41 ` [PATCH v4 04/19] hw/arm/aspeed: Add AST1700 LTPI expander device model Kane Chen via
@ 2025-12-24 10:38 ` Cédric Le Goater
2025-12-29 19:37 ` Nabih Estefan
1 sibling, 0 replies; 74+ messages in thread
From: Cédric Le Goater @ 2025-12-24 10:38 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan
On 12/24/25 02:41, Kane Chen via wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Introduce a minimal QEMU device model for the ASPEED AST1700, an
> MCU-less I/O expander used in the LTPI topology defined by the
> DC-SCM 2.0 specification (see figure 2):
> https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
>
> This initial implementation includes:
>
> * Definition of aspeed.ast1700 as a SysBusDevice
>
> * Setup of a basic memory region to reserve I/O space for future
> peripheral modeling
>
> This stub establishes the foundation for LTPI-related device emulation,
> without implementing any functional peripherals at this stage.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> include/hw/arm/aspeed_ast1700.h | 23 ++++++++++++++++
> hw/arm/aspeed_ast1700.c | 47 +++++++++++++++++++++++++++++++++
> hw/arm/meson.build | 1 +
> 3 files changed, 71 insertions(+)
> create mode 100644 include/hw/arm/aspeed_ast1700.h
> create mode 100644 hw/arm/aspeed_ast1700.c
>
> diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
> new file mode 100644
> index 0000000000..2a95ebfe89
> --- /dev/null
> +++ b/include/hw/arm/aspeed_ast1700.h
> @@ -0,0 +1,23 @@
> +/*
> + * ASPEED AST1700 IO Expander
> + *
> + * Copyright (C) 2025 ASPEED Technology Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +#ifndef ASPEED_AST1700_H
> +#define ASPEED_AST1700_H
> +
> +#include "hw/sysbus.h"
> +
> +#define TYPE_ASPEED_AST1700 "aspeed.ast1700"
> +
> +OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700)
> +
> +struct AspeedAST1700SoCState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion iomem;
> +};
> +
> +#endif /* ASPEED_AST1700_H */
> diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
> new file mode 100644
> index 0000000000..bb6ca2ce9e
> --- /dev/null
> +++ b/hw/arm/aspeed_ast1700.c
> @@ -0,0 +1,47 @@
> +/*
> + * ASPEED AST1700 IO Expander
> + *
> + * Copyright (C) 2025 ASPEED Technology Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/boards.h"
> +#include "hw/qdev-core.h"
> +#include "qom/object.h"
> +#include "hw/arm/aspeed_ast1700.h"
> +
> +#define AST2700_SOC_LTPI_SIZE 0x01000000
> +
> +static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> +{
> + AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> +
> + /* Occupy memory space for all controllers in AST1700 */
> + memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700,
> + AST2700_SOC_LTPI_SIZE);
> + sysbus_init_mmio(sbd, &s->iomem);
> +}
> +
> +static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->realize = aspeed_ast1700_realize;
> +}
> +
> +static const TypeInfo aspeed_ast1700_info = {
> + .name = TYPE_ASPEED_AST1700,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(AspeedAST1700SoCState),
> + .class_init = aspeed_ast1700_class_init,
> +};
> +
> +static void aspeed_ast1700_register_types(void)
> +{
> + type_register_static(&aspeed_ast1700_info);
> +}
> +
> +type_init(aspeed_ast1700_register_types);
> diff --git a/hw/arm/meson.build b/hw/arm/meson.build
> index aeaf654790..175942263d 100644
> --- a/hw/arm/meson.build
> +++ b/hw/arm/meson.build
> @@ -70,6 +70,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> 'aspeed_ast10x0_evb.c',
> 'fby35.c'))
> arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
> + 'aspeed_ast1700.c',
> 'aspeed_ast27x0.c',
> 'aspeed_ast27x0_evb.c',
> 'aspeed_ast27x0-fc.c',
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-12-24 1:41 ` [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700 Kane Chen via
@ 2025-12-24 10:39 ` Cédric Le Goater
2025-12-29 19:37 ` Nabih Estefan
2025-12-24 10:57 ` Cédric Le Goater
1 sibling, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2025-12-24 10:39 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan
On 12/24/25 02:41, Kane Chen via wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the AST1700 interrupt lines to the GIC in AST27X0, enabling
> the propagation of AST1700-originated interrupts to the host SoC.
>
> This patch does not implement interrupt sources in AST1700 itself,
> only the wiring into AST27X0.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> include/hw/arm/aspeed_soc.h | 6 +++-
> include/hw/intc/aspeed_intc.h | 2 ++
> hw/arm/aspeed_ast27x0.c | 37 +++++++++++++++++++++
> hw/intc/aspeed_intc.c | 60 +++++++++++++++++++++++++++++++++++
> 4 files changed, 104 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index f19bab3457..b051d0eb3a 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -58,6 +58,7 @@
> #define ASPEED_UARTS_NUM 13
> #define ASPEED_JTAG_NUM 2
> #define ASPEED_PCIE_NUM 3
> +#define ASPEED_INTC_NUM 2
> #define ASPEED_IOEXP_NUM 2
>
> struct AspeedSoCState {
> @@ -146,7 +147,8 @@ struct Aspeed27x0SoCState {
> AspeedSoCState parent;
>
> ARMCPU cpu[ASPEED_CPUS_NUM];
> - AspeedINTCState intc[2];
> + AspeedINTCState intc[ASPEED_INTC_NUM];
> + AspeedINTCState intcioexp[ASPEED_IOEXP_NUM];
> GICv3State gic;
> MemoryRegion dram_empty;
> };
> @@ -288,6 +290,8 @@ enum {
> ASPEED_DEV_LTPI_CTRL2,
> ASPEED_DEV_LTPI_IO0,
> ASPEED_DEV_LTPI_IO1,
> + ASPEED_DEV_IOEXP0_INTCIO,
> + ASPEED_DEV_IOEXP1_INTCIO,
> };
>
> const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
> diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
> index 51288384a5..4565bbab84 100644
> --- a/include/hw/intc/aspeed_intc.h
> +++ b/include/hw/intc/aspeed_intc.h
> @@ -15,6 +15,8 @@
> #define TYPE_ASPEED_INTC "aspeed.intc"
> #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
> #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
> +#define TYPE_ASPEED_2700_INTCIOEXP1 TYPE_ASPEED_INTC "ast2700-ioexp1"
> +#define TYPE_ASPEED_2700_INTCIOEXP2 TYPE_ASPEED_INTC "ast2700-ioexp2"
> #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
> #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp"
> #define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp"
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index de39a3e7eb..678d4eb6d9 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -91,7 +91,9 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_LTPI_CTRL2] = 0x14C35000,
> [ASPEED_DEV_WDT] = 0x14C37000,
> [ASPEED_DEV_LTPI_IO0] = 0x30000000,
> + [ASPEED_DEV_IOEXP0_INTCIO] = 0x30C18000,
> [ASPEED_DEV_LTPI_IO1] = 0x50000000,
> + [ASPEED_DEV_IOEXP1_INTCIO] = 0x50C18000,
> [ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
> [ASPEED_DEV_PCIE_MMIO1] = 0x80000000,
> [ASPEED_DEV_PCIE_MMIO2] = 0xA0000000,
> @@ -511,6 +513,10 @@ static void aspeed_soc_ast2700_init(Object *obj)
> object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC);
> object_initialize_child(obj, "intcio", &a->intc[1],
> TYPE_ASPEED_2700_INTCIO);
> + object_initialize_child(obj, "intcioexp0", &a->intcioexp[0],
> + TYPE_ASPEED_2700_INTCIOEXP1);
> + object_initialize_child(obj, "intcioexp1", &a->intcioexp[1],
> + TYPE_ASPEED_2700_INTCIOEXP2);
>
> snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
> object_initialize_child(obj, "adc", &s->adc, typename);
> @@ -755,6 +761,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0,
> sc->memmap[ASPEED_DEV_INTCIO]);
>
> + /* INTCIOEXP0 */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[0]), errp)) {
> + return;
> + }
> +
> + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[0]), 0,
> + sc->memmap[ASPEED_DEV_IOEXP0_INTCIO]);
> +
> + /* INTCIOEXP1 */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[1]), errp)) {
> + return;
> + }
> +
> + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[1]), 0,
> + sc->memmap[ASPEED_DEV_IOEXP1_INTCIO]);
> +
> /* irq sources -> orgates -> INTC */
> for (i = 0; i < ic->num_inpins; i++) {
> qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
> @@ -1079,6 +1101,21 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> }
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0,
> sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
> +
> + icio = ASPEED_INTC_GET_CLASS(&a->intcioexp[i]);
> + /* INTC_IOEXP internal: orgate[i] -> input[i] */
> + for (int j = 0; j < icio->num_inpins; j++) {
> + irq = qdev_get_gpio_in(DEVICE(&a->intcioexp[i]), j);
> + qdev_connect_gpio_out(DEVICE(&a->intcioexp[i].orgates[j]), 0,
> + irq);
> + }
> +
> + /* INTC_IOEXP output[i] -> INTC0.orgate[0].input[i] */
> + for (int j = 0; j < icio->num_outpins; j++) {
> + irq = qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), j);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&a->intcioexp[i]), j,
> + irq);
> + }
> }
>
> aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
> diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
> index 5cd786dee6..a04005ee7c 100644
> --- a/hw/intc/aspeed_intc.c
> +++ b/hw/intc/aspeed_intc.c
> @@ -924,6 +924,64 @@ static const TypeInfo aspeed_2700_intc_info = {
> .class_init = aspeed_2700_intc_class_init,
> };
>
> +static AspeedINTCIRQ aspeed_2700_intcioexp2_irqs[ASPEED_INTC_MAX_INPINS] = {
> + {0, 8, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> + {1, 9, 1, R_GICINT193_EN, R_GICINT193_STATUS},
> +};
> +
> +static void aspeed_2700_intcioexp2_class_init(ObjectClass *klass,
> + const void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
> +
> + dc->desc = "ASPEED 2700 IOEXP2 INTC Controller";
> + aic->num_lines = 32;
> + aic->num_inpins = 2;
> + aic->num_outpins = 10;
> + aic->mem_size = 0x400;
> + aic->nr_regs = 0x58 >> 2;
> + aic->reg_offset = 0x100;
> + aic->reg_ops = &aspeed_intcio_ops;
> + aic->irq_table = aspeed_2700_intcioexp2_irqs;
> + aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcioexp2_irqs);
> +}
> +
> +static const TypeInfo aspeed_2700_intcioexp2_info = {
> + .name = TYPE_ASPEED_2700_INTCIOEXP2,
> + .parent = TYPE_ASPEED_INTC,
> + .class_init = aspeed_2700_intcioexp2_class_init,
> +};
> +
> +static AspeedINTCIRQ aspeed_2700_intcioexp1_irqs[ASPEED_INTC_MAX_INPINS] = {
> + {0, 6, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> + {1, 7, 1, R_GICINT193_EN, R_GICINT193_STATUS},
> +};
> +
> +static void aspeed_2700_intcioexp1_class_init(ObjectClass *klass,
> + const void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
> +
> + dc->desc = "ASPEED 2700 IOEXP1 INTC Controller";
> + aic->num_lines = 32;
> + aic->num_inpins = 2;
> + aic->num_outpins = 10;
> + aic->mem_size = 0x400;
> + aic->nr_regs = 0x58 >> 2;
> + aic->reg_offset = 0x100;
> + aic->reg_ops = &aspeed_intcio_ops;
> + aic->irq_table = aspeed_2700_intcioexp1_irqs;
> + aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcioexp1_irqs);
> +}
> +
> +static const TypeInfo aspeed_2700_intcioexp1_info = {
> + .name = TYPE_ASPEED_2700_INTCIOEXP1,
> + .parent = TYPE_ASPEED_INTC,
> + .class_init = aspeed_2700_intcioexp1_class_init,
> +};
> +
> static AspeedINTCIRQ aspeed_2700_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
> {0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> {1, 1, 1, R_GICINT193_EN, R_GICINT193_STATUS},
> @@ -1099,6 +1157,8 @@ static void aspeed_intc_register_types(void)
> type_register_static(&aspeed_intc_info);
> type_register_static(&aspeed_2700_intc_info);
> type_register_static(&aspeed_2700_intcio_info);
> + type_register_static(&aspeed_2700_intcioexp1_info);
> + type_register_static(&aspeed_2700_intcioexp2_info);
> type_register_static(&aspeed_2700ssp_intc_info);
> type_register_static(&aspeed_2700ssp_intcio_info);
> type_register_static(&aspeed_2700tsp_intc_info);
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 07/19] hw/arm/aspeed: Attach LTPI controller to AST1700 model
2025-12-24 1:41 ` [PATCH v4 07/19] hw/arm/aspeed: Attach LTPI controller to AST1700 model Kane Chen via
@ 2025-12-24 10:41 ` Cédric Le Goater
2025-12-29 19:38 ` Nabih Estefan
0 siblings, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2025-12-24 10:41 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan
On 12/24/25 02:41, Kane Chen via wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the LTPI controller to the AST1700 model by mapping its MMIO
> region.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
> ---
> include/hw/arm/aspeed_ast1700.h | 3 +++
> hw/arm/aspeed_ast1700.c | 27 +++++++++++++++++++++++++++
> 2 files changed, 30 insertions(+)
>
> diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
> index 2a95ebfe89..b9ee4952d0 100644
> --- a/include/hw/arm/aspeed_ast1700.h
> +++ b/include/hw/arm/aspeed_ast1700.h
> @@ -9,6 +9,7 @@
> #define ASPEED_AST1700_H
>
> #include "hw/sysbus.h"
> +#include "hw/misc/aspeed_ltpi.h"
>
> #define TYPE_ASPEED_AST1700 "aspeed.ast1700"
>
> @@ -18,6 +19,8 @@ struct AspeedAST1700SoCState {
> SysBusDevice parent_obj;
>
> MemoryRegion iomem;
> +
> + AspeedLTPIState ltpi;
> };
>
> #endif /* ASPEED_AST1700_H */
> diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
> index bb6ca2ce9e..eeb586102f 100644
> --- a/hw/arm/aspeed_ast1700.c
> +++ b/hw/arm/aspeed_ast1700.c
> @@ -14,6 +14,14 @@
>
> #define AST2700_SOC_LTPI_SIZE 0x01000000
>
> +enum {
> + ASPEED_AST1700_DEV_LTPI_CTRL,
> +};
> +
> +static const hwaddr aspeed_ast1700_io_memmap[] = {
> + [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> +};
> +
> static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> {
> AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
> @@ -23,8 +31,26 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700,
> AST2700_SOC_LTPI_SIZE);
> sysbus_init_mmio(sbd, &s->iomem);
> +
> + /* LTPI controller */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
> + return;
> + }
> + memory_region_add_subregion(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_CTRL],
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0));
> }
>
> +static void aspeed_ast1700_instance_init(Object *obj)
> +{
> + AspeedAST1700SoCState *s = ASPEED_AST1700(obj);
> +
> + /* LTPI controller */
> + object_initialize_child(obj, "ltpi-ctrl",
> + &s->ltpi, TYPE_ASPEED_LTPI);
> +
> + return;
> +}
> static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -37,6 +63,7 @@ static const TypeInfo aspeed_ast1700_info = {
> .parent = TYPE_SYS_BUS_DEVICE,
> .instance_size = sizeof(AspeedAST1700SoCState),
> .class_init = aspeed_ast1700_class_init,
> + .instance_init = aspeed_ast1700_instance_init,
> };
>
> static void aspeed_ast1700_register_types(void)
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 18/19] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device
2025-12-24 1:41 ` [PATCH v4 18/19] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device Kane Chen via
@ 2025-12-24 10:43 ` Cédric Le Goater
2025-12-29 19:38 ` Nabih Estefan
0 siblings, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2025-12-24 10:43 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan
On 12/24/25 02:41, Kane Chen via wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> AST1700 exposes more I3C buses than the current dummy I3C model
> provides. When Linux probes the I3C devices on AST1700 this mismatch
> can trigger a kernel panic. Model the I3C block as an unimplemented
> device to make the missing functionality explicit and avoid unexpected
> side effects.
>
> This wires up the I3C interrupt lines for the IO expanders and adds the
> corresponding device entries for the AST1700 model.
>
> No functional I3C emulation is provided yet; this only prevents crashes and
> documents the missing piece.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> include/hw/arm/aspeed_ast1700.h | 3 +++
> include/hw/arm/aspeed_soc.h | 2 ++
> hw/arm/aspeed_ast1700.c | 15 +++++++++++++++
> hw/arm/aspeed_ast27x0.c | 18 ++++++++++++++++--
> 4 files changed, 36 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
> index 490f2a3b05..874b4d63fe 100644
> --- a/include/hw/arm/aspeed_ast1700.h
> +++ b/include/hw/arm/aspeed_ast1700.h
> @@ -19,6 +19,7 @@
> #include "hw/ssi/aspeed_smc.h"
> #include "hw/watchdog/wdt_aspeed.h"
> #include "hw/char/serial-mm.h"
> +#include "hw/misc/unimp.h"
>
> #define AST1700_SGPIO_NUM 2
> #define AST1700_WDT_NUM 9
> @@ -45,6 +46,8 @@ struct AspeedAST1700SoCState {
> AspeedI2CState i2c;
> AspeedPWMState pwm;
> AspeedWDTState wdt[AST1700_WDT_NUM];
> +
> + UnimplementedDeviceState i3c;
> };
>
> #endif /* ASPEED_AST1700_H */
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 4ea2521041..b185b04186 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -294,6 +294,8 @@ enum {
> ASPEED_DEV_IOEXP1_I2C,
> ASPEED_DEV_IOEXP0_INTCIO,
> ASPEED_DEV_IOEXP1_INTCIO,
> + ASPEED_DEV_IOEXP0_I3C,
> + ASPEED_DEV_IOEXP1_I3C,
> };
>
> const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
> diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
> index ca0ce4e2c2..5f3c56e6cc 100644
> --- a/hw/arm/aspeed_ast1700.c
> +++ b/hw/arm/aspeed_ast1700.c
> @@ -15,6 +15,7 @@
>
> #define AST2700_SOC_LTPI_SIZE 0x01000000
> #define AST1700_SOC_SRAM_SIZE 0x00040000
> +#define AST1700_SOC_I3C_SIZE 0x00010000
>
> enum {
> ASPEED_AST1700_DEV_SPI0,
> @@ -26,6 +27,7 @@ enum {
> ASPEED_AST1700_DEV_SGPIOM0,
> ASPEED_AST1700_DEV_SGPIOM1,
> ASPEED_AST1700_DEV_I2C,
> + ASPEED_AST1700_DEV_I3C,
> ASPEED_AST1700_DEV_UART12,
> ASPEED_AST1700_DEV_LTPI_CTRL,
> ASPEED_AST1700_DEV_WDT,
> @@ -42,6 +44,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
> [ASPEED_AST1700_DEV_SGPIOM0] = 0x00C0C000,
> [ASPEED_AST1700_DEV_SGPIOM1] = 0x00C0D000,
> [ASPEED_AST1700_DEV_I2C] = 0x00C0F000,
> + [ASPEED_AST1700_DEV_I3C] = 0x00C20000,
> [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> [ASPEED_AST1700_DEV_WDT] = 0x00C37000,
> @@ -172,6 +175,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->wdt[i]), 0));
> }
>
> + /* I3C */
> + qdev_prop_set_string(DEVICE(&s->i3c), "name", "ioexp-i3c");
> + qdev_prop_set_uint64(DEVICE(&s->i3c), "size", AST1700_SOC_I3C_SIZE);
> + sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp);
> + memory_region_add_subregion_overlap(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I3C],
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i3c), 0),
> + -1000);
> }
>
> static void aspeed_ast1700_instance_init(Object *obj)
> @@ -221,6 +232,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
> &s->wdt[i], "aspeed.wdt-ast2700");
> }
>
> + /* I3C */
> + object_initialize_child(obj, "ioexp-i3c[*]", &s->i3c,
> + TYPE_UNIMPLEMENTED_DEVICE);
> +
> return;
> }
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index ca3adf9a50..0807481162 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -206,7 +206,9 @@ static const int aspeed_soc_ast2700a1_irqmap[] = {
> [ASPEED_DEV_PECI] = 197,
> [ASPEED_DEV_SDHCI] = 197,
> [ASPEED_DEV_IOEXP0_I2C] = 198,
> + [ASPEED_DEV_IOEXP0_I3C] = 199,
> [ASPEED_DEV_IOEXP1_I2C] = 200,
> + [ASPEED_DEV_IOEXP1_I3C] = 201,
> };
>
> /* GICINT 128 */
> @@ -275,12 +277,24 @@ static const int ast2700_gic198_intcmap[] = {
> [ASPEED_DEV_IOEXP0_I2C] = 0, /* 0 - 15 */
> };
>
> +/* Primary AST1700 Interrupts */
> +/* A1: GINTC 199 */
> +static const int ast2700_gic199_intcmap[] = {
> + [ASPEED_DEV_IOEXP0_I3C] = 0, /* 0 - 15 */
> +};
> +
> /* Secondary AST1700 Interrupts */
> /* A1: GINTC 200 */
> static const int ast2700_gic200_intcmap[] = {
> [ASPEED_DEV_IOEXP1_I2C] = 0, /* 0 - 15 */
> };
>
> +/* Secondary AST1700 Interrupts */
> +/* A1: GINTC 201 */
> +static const int ast2700_gic201_intcmap[] = {
> + [ASPEED_DEV_IOEXP1_I3C] = 0, /* 0 - 15 */
> +};
> +
> /* GICINT 128 ~ 136 */
> /* GICINT 192 ~ 201 */
> struct gic_intc_irq_info {
> @@ -298,9 +312,9 @@ static const struct gic_intc_irq_info ast2700_gic_intcmap[] = {
> {196, 1, 4, ast2700_gic132_gic196_intcmap},
> {197, 1, 5, ast2700_gic133_gic197_intcmap},
> {198, 2, 0, ast2700_gic198_intcmap},
> - {199, 1, 7, NULL},
> + {199, 2, 1, ast2700_gic199_intcmap},
> {200, 3, 0, ast2700_gic200_intcmap},
> - {201, 1, 9, NULL},
> + {201, 3, 1, ast2700_gic201_intcmap},
> {128, 0, 1, ast2700_gic128_gic192_intcmap},
> {129, 0, 2, NULL},
> {130, 0, 3, ast2700_gic130_gic194_intcmap},
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 19/19] hw/arm/aspeed: Enable AST1700 IO expander support
2025-12-24 1:41 ` [PATCH v4 19/19] hw/arm/aspeed: Enable AST1700 IO expander support Kane Chen via
@ 2025-12-24 10:43 ` Cédric Le Goater
2025-12-29 19:38 ` Nabih Estefan
0 siblings, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2025-12-24 10:43 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan
On 12/24/25 02:41, Kane Chen via wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Set ioexp_num to 2 to enable AST1700 IO expander support.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> hw/arm/aspeed_ast27x0.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 0807481162..2eb857b8e0 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -1260,7 +1260,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
> sc->macs_num = 3;
> sc->uarts_num = 13;
> sc->num_cpus = 4;
> - sc->ioexp_num = 0;
> + sc->ioexp_num = 2;
> sc->uarts_base = ASPEED_DEV_UART0;
> sc->irqmap = aspeed_soc_ast2700a1_irqmap;
> sc->memmap = aspeed_soc_ast2700_memmap;
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-12-24 1:41 ` [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700 Kane Chen via
2025-12-24 10:39 ` Cédric Le Goater
@ 2025-12-24 10:57 ` Cédric Le Goater
2025-12-26 1:34 ` Kane Chen
1 sibling, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2025-12-24 10:57 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan
On 12/24/25 02:41, Kane Chen via wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the AST1700 interrupt lines to the GIC in AST27X0, enabling
> the propagation of AST1700-originated interrupts to the host SoC.
>
> This patch does not implement interrupt sources in AST1700 itself,
> only the wiring into AST27X0.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> include/hw/arm/aspeed_soc.h | 6 +++-
> include/hw/intc/aspeed_intc.h | 2 ++
> hw/arm/aspeed_ast27x0.c | 37 +++++++++++++++++++++
> hw/intc/aspeed_intc.c | 60 +++++++++++++++++++++++++++++++++++
> 4 files changed, 104 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index f19bab3457..b051d0eb3a 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -58,6 +58,7 @@
> #define ASPEED_UARTS_NUM 13
> #define ASPEED_JTAG_NUM 2
> #define ASPEED_PCIE_NUM 3
> +#define ASPEED_INTC_NUM 2
> #define ASPEED_IOEXP_NUM 2
>
> struct AspeedSoCState {
> @@ -146,7 +147,8 @@ struct Aspeed27x0SoCState {
> AspeedSoCState parent;
>
> ARMCPU cpu[ASPEED_CPUS_NUM];
> - AspeedINTCState intc[2];
> + AspeedINTCState intc[ASPEED_INTC_NUM];
> + AspeedINTCState intcioexp[ASPEED_IOEXP_NUM];
> GICv3State gic;
> MemoryRegion dram_empty;
> };
> @@ -288,6 +290,8 @@ enum {
> ASPEED_DEV_LTPI_CTRL2,
> ASPEED_DEV_LTPI_IO0,
> ASPEED_DEV_LTPI_IO1,
> + ASPEED_DEV_IOEXP0_INTCIO,
> + ASPEED_DEV_IOEXP1_INTCIO,
> };
>
> const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
> diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
> index 51288384a5..4565bbab84 100644
> --- a/include/hw/intc/aspeed_intc.h
> +++ b/include/hw/intc/aspeed_intc.h
> @@ -15,6 +15,8 @@
> #define TYPE_ASPEED_INTC "aspeed.intc"
> #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
> #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
> +#define TYPE_ASPEED_2700_INTCIOEXP1 TYPE_ASPEED_INTC "ast2700-ioexp1"
Adding a leading dash would improve readability
... TYPE_ASPEED_INTC "-ast2700-ioexp1"
> +#define TYPE_ASPEED_2700_INTCIOEXP2 TYPE_ASPEED_INTC "ast2700-ioexp2"
same here ^
> #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
> #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp"
> #define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp"
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index de39a3e7eb..678d4eb6d9 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -91,7 +91,9 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_LTPI_CTRL2] = 0x14C35000,
> [ASPEED_DEV_WDT] = 0x14C37000,
> [ASPEED_DEV_LTPI_IO0] = 0x30000000,
> + [ASPEED_DEV_IOEXP0_INTCIO] = 0x30C18000,
> [ASPEED_DEV_LTPI_IO1] = 0x50000000,
> + [ASPEED_DEV_IOEXP1_INTCIO] = 0x50C18000,
> [ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
> [ASPEED_DEV_PCIE_MMIO1] = 0x80000000,
> [ASPEED_DEV_PCIE_MMIO2] = 0xA0000000,
> @@ -511,6 +513,10 @@ static void aspeed_soc_ast2700_init(Object *obj)
> object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC);
> object_initialize_child(obj, "intcio", &a->intc[1],
> TYPE_ASPEED_2700_INTCIO);
> + object_initialize_child(obj, "intcioexp0", &a->intcioexp[0],
"intc-ioexp0" reads better,
> + TYPE_ASPEED_2700_INTCIOEXP1);
> + object_initialize_child(obj, "intcioexp1", &a->intcioexp[1],
and "intc-ioexp1" too.
I can fix the naming if you agree.
Thanks,
C.
> + TYPE_ASPEED_2700_INTCIOEXP2);
>
> snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
> object_initialize_child(obj, "adc", &s->adc, typename);
> @@ -755,6 +761,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0,
> sc->memmap[ASPEED_DEV_INTCIO]);
>
> + /* INTCIOEXP0 */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[0]), errp)) {
> + return;
> + }
> +
> + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[0]), 0,
> + sc->memmap[ASPEED_DEV_IOEXP0_INTCIO]);
> +
> + /* INTCIOEXP1 */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[1]), errp)) {
> + return;
> + }
> +
> + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[1]), 0,
> + sc->memmap[ASPEED_DEV_IOEXP1_INTCIO]);
> +
> /* irq sources -> orgates -> INTC */
> for (i = 0; i < ic->num_inpins; i++) {
> qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
> @@ -1079,6 +1101,21 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> }
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0,
> sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
> +
> + icio = ASPEED_INTC_GET_CLASS(&a->intcioexp[i]);
> + /* INTC_IOEXP internal: orgate[i] -> input[i] */
> + for (int j = 0; j < icio->num_inpins; j++) {
> + irq = qdev_get_gpio_in(DEVICE(&a->intcioexp[i]), j);
> + qdev_connect_gpio_out(DEVICE(&a->intcioexp[i].orgates[j]), 0,
> + irq);
> + }
> +
> + /* INTC_IOEXP output[i] -> INTC0.orgate[0].input[i] */
> + for (int j = 0; j < icio->num_outpins; j++) {
> + irq = qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), j);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&a->intcioexp[i]), j,
> + irq);
> + }
> }
>
> aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
> diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
> index 5cd786dee6..a04005ee7c 100644
> --- a/hw/intc/aspeed_intc.c
> +++ b/hw/intc/aspeed_intc.c
> @@ -924,6 +924,64 @@ static const TypeInfo aspeed_2700_intc_info = {
> .class_init = aspeed_2700_intc_class_init,
> };
>
> +static AspeedINTCIRQ aspeed_2700_intcioexp2_irqs[ASPEED_INTC_MAX_INPINS] = {
> + {0, 8, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> + {1, 9, 1, R_GICINT193_EN, R_GICINT193_STATUS},
> +};
> +
> +static void aspeed_2700_intcioexp2_class_init(ObjectClass *klass,
> + const void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
> +
> + dc->desc = "ASPEED 2700 IOEXP2 INTC Controller";
> + aic->num_lines = 32;
> + aic->num_inpins = 2;
> + aic->num_outpins = 10;
> + aic->mem_size = 0x400;
> + aic->nr_regs = 0x58 >> 2;
> + aic->reg_offset = 0x100;
> + aic->reg_ops = &aspeed_intcio_ops;
> + aic->irq_table = aspeed_2700_intcioexp2_irqs;
> + aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcioexp2_irqs);
> +}
> +
> +static const TypeInfo aspeed_2700_intcioexp2_info = {
> + .name = TYPE_ASPEED_2700_INTCIOEXP2,
> + .parent = TYPE_ASPEED_INTC,
> + .class_init = aspeed_2700_intcioexp2_class_init,
> +};
> +
> +static AspeedINTCIRQ aspeed_2700_intcioexp1_irqs[ASPEED_INTC_MAX_INPINS] = {
> + {0, 6, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> + {1, 7, 1, R_GICINT193_EN, R_GICINT193_STATUS},
> +};
> +
> +static void aspeed_2700_intcioexp1_class_init(ObjectClass *klass,
> + const void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
> +
> + dc->desc = "ASPEED 2700 IOEXP1 INTC Controller";
> + aic->num_lines = 32;
> + aic->num_inpins = 2;
> + aic->num_outpins = 10;
> + aic->mem_size = 0x400;
> + aic->nr_regs = 0x58 >> 2;
> + aic->reg_offset = 0x100;
> + aic->reg_ops = &aspeed_intcio_ops;
> + aic->irq_table = aspeed_2700_intcioexp1_irqs;
> + aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcioexp1_irqs);
> +}
> +
> +static const TypeInfo aspeed_2700_intcioexp1_info = {
> + .name = TYPE_ASPEED_2700_INTCIOEXP1,
> + .parent = TYPE_ASPEED_INTC,
> + .class_init = aspeed_2700_intcioexp1_class_init,
> +};
> +
> static AspeedINTCIRQ aspeed_2700_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
> {0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> {1, 1, 1, R_GICINT193_EN, R_GICINT193_STATUS},
> @@ -1099,6 +1157,8 @@ static void aspeed_intc_register_types(void)
> type_register_static(&aspeed_intc_info);
> type_register_static(&aspeed_2700_intc_info);
> type_register_static(&aspeed_2700_intcio_info);
> + type_register_static(&aspeed_2700_intcioexp1_info);
> + type_register_static(&aspeed_2700_intcioexp2_info);
> type_register_static(&aspeed_2700ssp_intc_info);
> type_register_static(&aspeed_2700ssp_intcio_info);
> type_register_static(&aspeed_2700tsp_intc_info);
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700 model
2025-12-24 1:41 ` [PATCH v4 14/19] hw/arm/aspeed: attach I2C " Kane Chen via
@ 2025-12-24 11:04 ` Cédric Le Goater
2026-01-07 14:53 ` Cédric Le Goater
1 sibling, 0 replies; 74+ messages in thread
From: Cédric Le Goater @ 2025-12-24 11:04 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan
On 12/24/25 02:41, Kane Chen via wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the I2C controller to the AST1700 model by mapping its MMIO
> region and wiring its interrupt line.
>
> This patch also adds a bus_label property to distinguish I2C buses on
> the BMC from those on external boards. This prevents user-specified
> I2C devices from being attached to the wrong bus when provided via CLI.
This patch does 2 things. Please split the changes and provide an
example of the bus name in the commit log.
I think we should add documentation for the IO expander and mention
the I2C bus names too.
Thanks,
C.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
> include/hw/arm/aspeed_ast1700.h | 2 ++
> include/hw/arm/aspeed_soc.h | 2 ++
> include/hw/i2c/aspeed_i2c.h | 1 +
> hw/arm/aspeed_ast1700.c | 18 ++++++++++++
> hw/arm/aspeed_ast27x0.c | 51 +++++++++++++++++++++++++++++++--
> hw/i2c/aspeed_i2c.c | 19 ++++++++++--
> 6 files changed, 88 insertions(+), 5 deletions(-)
>
> diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
> index 7ea6ff4c1a..d4b7abee7d 100644
> --- a/include/hw/arm/aspeed_ast1700.h
> +++ b/include/hw/arm/aspeed_ast1700.h
> @@ -12,6 +12,7 @@
> #include "hw/misc/aspeed_scu.h"
> #include "hw/adc/aspeed_adc.h"
> #include "hw/gpio/aspeed_gpio.h"
> +#include "hw/i2c/aspeed_i2c.h"
> #include "hw/misc/aspeed_ltpi.h"
> #include "hw/ssi/aspeed_smc.h"
> #include "hw/char/serial-mm.h"
> @@ -34,6 +35,7 @@ struct AspeedAST1700SoCState {
> AspeedADCState adc;
> AspeedSCUState scu;
> AspeedGPIOState gpio;
> + AspeedI2CState i2c;
> };
>
> #endif /* ASPEED_AST1700_H */
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index b051d0eb3a..4ea2521041 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -290,6 +290,8 @@ enum {
> ASPEED_DEV_LTPI_CTRL2,
> ASPEED_DEV_LTPI_IO0,
> ASPEED_DEV_LTPI_IO1,
> + ASPEED_DEV_IOEXP0_I2C,
> + ASPEED_DEV_IOEXP1_I2C,
> ASPEED_DEV_IOEXP0_INTCIO,
> ASPEED_DEV_IOEXP1_INTCIO,
> };
> diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
> index 2daacc10ce..babbad5ed9 100644
> --- a/include/hw/i2c/aspeed_i2c.h
> +++ b/include/hw/i2c/aspeed_i2c.h
> @@ -269,6 +269,7 @@ struct AspeedI2CState {
> uint32_t intr_status;
> uint32_t ctrl_global;
> uint32_t new_clk_divider;
> + char *bus_label;
> MemoryRegion pool_iomem;
> uint8_t share_pool[ASPEED_I2C_SHARE_POOL_SIZE];
>
> diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
> index 9a6019908e..fad3b86e8d 100644
> --- a/hw/arm/aspeed_ast1700.c
> +++ b/hw/arm/aspeed_ast1700.c
> @@ -22,6 +22,7 @@ enum {
> ASPEED_AST1700_DEV_ADC,
> ASPEED_AST1700_DEV_SCU,
> ASPEED_AST1700_DEV_GPIO,
> + ASPEED_AST1700_DEV_I2C,
> ASPEED_AST1700_DEV_UART12,
> ASPEED_AST1700_DEV_LTPI_CTRL,
> ASPEED_AST1700_DEV_SPI0_MEM,
> @@ -33,6 +34,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
> [ASPEED_AST1700_DEV_ADC] = 0x00C00000,
> [ASPEED_AST1700_DEV_SCU] = 0x00C02000,
> [ASPEED_AST1700_DEV_GPIO] = 0x00C0B000,
> + [ASPEED_AST1700_DEV_I2C] = 0x00C0F000,
> [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> [ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
> @@ -108,6 +110,18 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_GPIO],
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0));
>
> + /* I2C */
> + snprintf(dev_name, sizeof(dev_name), "ioexp%d", s->board_idx);
> + qdev_prop_set_string(DEVICE(&s->i2c), "bus-label", dev_name);
> + object_property_set_link(OBJECT(&s->i2c), "dram",
> + OBJECT(&s->iomem), errp);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
> + return;
> + }
> + memory_region_add_subregion(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I2C],
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c), 0));
> +
> /* LTPI controller */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
> return;
> @@ -141,6 +155,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
> object_initialize_child(obj, "ioexp-gpio[*]", &s->gpio,
> "aspeed.gpio-ast2700");
>
> + /* I2C */
> + object_initialize_child(obj, "ioexp-i2c[*]", &s->i2c,
> + "aspeed.i2c-ast2700");
> +
> /* LTPI controller */
> object_initialize_child(obj, "ltpi-ctrl",
> &s->ltpi, TYPE_ASPEED_LTPI);
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index d998326536..ca3adf9a50 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -205,6 +205,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] = {
> [ASPEED_DEV_ETH3] = 196,
> [ASPEED_DEV_PECI] = 197,
> [ASPEED_DEV_SDHCI] = 197,
> + [ASPEED_DEV_IOEXP0_I2C] = 198,
> + [ASPEED_DEV_IOEXP1_I2C] = 200,
> };
>
> /* GICINT 128 */
> @@ -267,6 +269,18 @@ static const int ast2700_gic133_gic197_intcmap[] = {
> [ASPEED_DEV_PECI] = 4,
> };
>
> +/* Primary AST1700 Interrupts */
> +/* A1: GICINT 198 */
> +static const int ast2700_gic198_intcmap[] = {
> + [ASPEED_DEV_IOEXP0_I2C] = 0, /* 0 - 15 */
> +};
> +
> +/* Secondary AST1700 Interrupts */
> +/* A1: GINTC 200 */
> +static const int ast2700_gic200_intcmap[] = {
> + [ASPEED_DEV_IOEXP1_I2C] = 0, /* 0 - 15 */
> +};
> +
> /* GICINT 128 ~ 136 */
> /* GICINT 192 ~ 201 */
> struct gic_intc_irq_info {
> @@ -283,9 +297,9 @@ static const struct gic_intc_irq_info ast2700_gic_intcmap[] = {
> {195, 1, 3, ast2700_gic131_gic195_intcmap},
> {196, 1, 4, ast2700_gic132_gic196_intcmap},
> {197, 1, 5, ast2700_gic133_gic197_intcmap},
> - {198, 1, 6, NULL},
> + {198, 2, 0, ast2700_gic198_intcmap},
> {199, 1, 7, NULL},
> - {200, 1, 8, NULL},
> + {200, 3, 0, ast2700_gic200_intcmap},
> {201, 1, 9, NULL},
> {128, 0, 1, ast2700_gic128_gic192_intcmap},
> {129, 0, 2, NULL},
> @@ -327,14 +341,23 @@ static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev,
> int or_idx;
> int idx;
> int i;
> + OrIRQState *porgates;
>
> for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
> if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
> assert(ast2700_gic_intcmap[i].ptr);
> or_idx = ast2700_gic_intcmap[i].orgate_idx;
> idx = ast2700_gic_intcmap[i].intc_idx;
> - return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
> + if (idx < ASPEED_INTC_NUM) {
> + porgates = &a->intc[idx].orgates[or_idx];
> + return qdev_get_gpio_in(DEVICE(porgates),
> + ast2700_gic_intcmap[i].ptr[dev] + index);
> + } else {
> + idx -= ASPEED_INTC_NUM;
> + porgates = &a->intcioexp[idx].orgates[or_idx];
> + return qdev_get_gpio_in(DEVICE(porgates),
> ast2700_gic_intcmap[i].ptr[dev] + index);
> + }
> }
> }
>
> @@ -1098,6 +1121,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
>
> /* IO Expander */
> for (i = 0; i < sc->ioexp_num; i++) {
> + AspeedI2CClass *i2c_ctl;
> +
> qdev_prop_set_uint8(DEVICE(&s->ioexp[i]), "board-idx", i);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) {
> return;
> @@ -1128,6 +1153,26 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].gpio), 0,
> aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO));
>
> + /* I2C */
> + i2c_ctl = ASPEED_I2C_GET_CLASS(&s->ioexp[i].i2c);
> + for (int j = 0; j < i2c_ctl->num_busses; j++) {
> + /*
> + * For I2C on AST1700:
> + * I2C bus interrupts are connected to the OR gate from bit 0 to bit
> + * 15, and the OR gate output pin is connected to the input pin of
> + * GICINT192 of IO expander Interrupt controller (INTC2/3). Then,
> + * the output pin is connected to the INTC (CPU Die) input pin, and
> + * its output pin is connected to the GIC.
> + *
> + * I2C bus 0 is connected to the OR gate at bit 0.
> + * I2C bus 15 is connected to the OR gate at bit 15.
> + */
> + irq = aspeed_soc_ast2700_get_irq_index(s,
> + ASPEED_DEV_IOEXP0_I2C + i,
> + j);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].i2c.busses[j]),
> + 0, irq);
> + }
> }
>
> aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
> diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
> index 83fb906bdc..ca84068bb4 100644
> --- a/hw/i2c/aspeed_i2c.c
> +++ b/hw/i2c/aspeed_i2c.c
> @@ -1261,6 +1261,7 @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
> static const Property aspeed_i2c_properties[] = {
> DEFINE_PROP_LINK("dram", AspeedI2CState, dram_mr,
> TYPE_MEMORY_REGION, MemoryRegion *),
> + DEFINE_PROP_STRING("bus-label", AspeedI2CState, bus_label),
> };
>
> static void aspeed_i2c_class_init(ObjectClass *klass, const void *data)
> @@ -1421,14 +1422,28 @@ static void aspeed_i2c_bus_realize(DeviceState *dev, Error **errp)
> {
> AspeedI2CBus *s = ASPEED_I2C_BUS(dev);
> AspeedI2CClass *aic;
> - g_autofree char *name = g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s->id);
> - g_autofree char *pool_name = g_strdup_printf("%s.pool", name);
> + g_autofree char *name = NULL;
> + g_autofree char *pool_name = NULL;
>
> if (!s->controller) {
> error_setg(errp, TYPE_ASPEED_I2C_BUS ": 'controller' link not set");
> return;
> }
>
> + /*
> + * I2C bus naming:
> + * - Empty bus_label -> BMC internal controller, use default name.
> + * - Non-empty bus_label -> external/addon controller, prefix with label
> + * to avoid conflicts and show bus origin.
> + */
> + if (!s->controller->bus_label || (strlen(s->controller->bus_label) == 0)) {
> + name = g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s->id);
> + } else {
> + name = g_strdup_printf("aspeed.%s.i2c.bus.%d",
> + s->controller->bus_label, s->id);
> + }
> + pool_name = g_strdup_printf("%s.pool", name);
> +
> aic = ASPEED_I2C_GET_CLASS(s->controller);
>
> sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
^ permalink raw reply [flat|nested] 74+ messages in thread
* RE: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-12-24 10:57 ` Cédric Le Goater
@ 2025-12-26 1:34 ` Kane Chen
2025-12-27 17:50 ` Cédric Le Goater
0 siblings, 1 reply; 74+ messages in thread
From: Kane Chen @ 2025-12-26 1:34 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, nabihestefan@google.com
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Wednesday, December 24, 2025 6:58 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; nabihestefan@google.com
> Subject: Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller
> for AST1700
>
> On 12/24/25 02:41, Kane Chen via wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > Connect the AST1700 interrupt lines to the GIC in AST27X0, enabling
> > the propagation of AST1700-originated interrupts to the host SoC.
> >
> > This patch does not implement interrupt sources in AST1700 itself,
> > only the wiring into AST27X0.
> >
> > Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> > ---
> > include/hw/arm/aspeed_soc.h | 6 +++-
> > include/hw/intc/aspeed_intc.h | 2 ++
> > hw/arm/aspeed_ast27x0.c | 37 +++++++++++++++++++++
> > hw/intc/aspeed_intc.c | 60
> +++++++++++++++++++++++++++++++++++
> > 4 files changed, 104 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> > index f19bab3457..b051d0eb3a 100644
> > --- a/include/hw/arm/aspeed_soc.h
> > +++ b/include/hw/arm/aspeed_soc.h
> > @@ -58,6 +58,7 @@
> > #define ASPEED_UARTS_NUM 13
> > #define ASPEED_JTAG_NUM 2
> > #define ASPEED_PCIE_NUM 3
> > +#define ASPEED_INTC_NUM 2
> > #define ASPEED_IOEXP_NUM 2
> >
> > struct AspeedSoCState {
> > @@ -146,7 +147,8 @@ struct Aspeed27x0SoCState {
> > AspeedSoCState parent;
> >
> > ARMCPU cpu[ASPEED_CPUS_NUM];
> > - AspeedINTCState intc[2];
> > + AspeedINTCState intc[ASPEED_INTC_NUM];
> > + AspeedINTCState intcioexp[ASPEED_IOEXP_NUM];
> > GICv3State gic;
> > MemoryRegion dram_empty;
> > };
> > @@ -288,6 +290,8 @@ enum {
> > ASPEED_DEV_LTPI_CTRL2,
> > ASPEED_DEV_LTPI_IO0,
> > ASPEED_DEV_LTPI_IO1,
> > + ASPEED_DEV_IOEXP0_INTCIO,
> > + ASPEED_DEV_IOEXP1_INTCIO,
> > };
> >
> > const char *aspeed_soc_cpu_type(const char * const
> > *valid_cpu_types); diff --git a/include/hw/intc/aspeed_intc.h
> > b/include/hw/intc/aspeed_intc.h index 51288384a5..4565bbab84 100644
> > --- a/include/hw/intc/aspeed_intc.h
> > +++ b/include/hw/intc/aspeed_intc.h
> > @@ -15,6 +15,8 @@
> > #define TYPE_ASPEED_INTC "aspeed.intc"
> > #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
> > #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
> > +#define TYPE_ASPEED_2700_INTCIOEXP1 TYPE_ASPEED_INTC
> "ast2700-ioexp1"
>
> Adding a leading dash would improve readability
>
> ... TYPE_ASPEED_INTC "-ast2700-ioexp1"
>
> > +#define TYPE_ASPEED_2700_INTCIOEXP2 TYPE_ASPEED_INTC
> "ast2700-ioexp2"
>
> same here ^
>
>
> > #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
> > #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC
> "io-ast2700ssp"
> > #define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp"
> > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index
> > de39a3e7eb..678d4eb6d9 100644
> > --- a/hw/arm/aspeed_ast27x0.c
> > +++ b/hw/arm/aspeed_ast27x0.c
> > @@ -91,7 +91,9 @@ static const hwaddr aspeed_soc_ast2700_memmap[]
> = {
> > [ASPEED_DEV_LTPI_CTRL2] = 0x14C35000,
> > [ASPEED_DEV_WDT] = 0x14C37000,
> > [ASPEED_DEV_LTPI_IO0] = 0x30000000,
> > + [ASPEED_DEV_IOEXP0_INTCIO] = 0x30C18000,
> > [ASPEED_DEV_LTPI_IO1] = 0x50000000,
> > + [ASPEED_DEV_IOEXP1_INTCIO] = 0x50C18000,
> > [ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
> > [ASPEED_DEV_PCIE_MMIO1] = 0x80000000,
> > [ASPEED_DEV_PCIE_MMIO2] = 0xA0000000, @@ -511,6 +513,10
> @@
> > static void aspeed_soc_ast2700_init(Object *obj)
> > object_initialize_child(obj, "intc", &a->intc[0],
> TYPE_ASPEED_2700_INTC);
> > object_initialize_child(obj, "intcio", &a->intc[1],
> > TYPE_ASPEED_2700_INTCIO);
> > + object_initialize_child(obj, "intcioexp0", &a->intcioexp[0],
>
> "intc-ioexp0" reads better,
>
> > + TYPE_ASPEED_2700_INTCIOEXP1);
> > + object_initialize_child(obj, "intcioexp1", &a->intcioexp[1],
>
> and "intc-ioexp1" too.
>
> I can fix the naming if you agree.
>
> Thanks,
>
> C.
Hi Cédric,
Thank you for the suggestion. Since I need to submit a v5 patch to split the I2C
code changes anyway, I will handle the naming adjustments and other minor fixes
myself in that version.
Thanks again for your feedback and review!
Best Regards,
Kane
>
> > + TYPE_ASPEED_2700_INTCIOEXP2);
> >
> > snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
> > object_initialize_child(obj, "adc", &s->adc, typename); @@
> > -755,6 +761,22 @@ static void aspeed_soc_ast2700_realize(DeviceState
> *dev, Error **errp)
> > aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0,
> > sc->memmap[ASPEED_DEV_INTCIO]);
> >
> > + /* INTCIOEXP0 */
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[0]), errp)) {
> > + return;
> > + }
> > +
> > + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[0]),
> 0,
> > + sc->memmap[ASPEED_DEV_IOEXP0_INTCIO]);
> > +
> > + /* INTCIOEXP1 */
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[1]), errp)) {
> > + return;
> > + }
> > +
> > + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[1]),
> 0,
> > + sc->memmap[ASPEED_DEV_IOEXP1_INTCIO]);
> > +
> > /* irq sources -> orgates -> INTC */
> > for (i = 0; i < ic->num_inpins; i++) {
> > qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, @@
> > -1079,6 +1101,21 @@ static void aspeed_soc_ast2700_realize(DeviceState
> *dev, Error **errp)
> > }
> > sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0,
> > sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
> > +
> > + icio = ASPEED_INTC_GET_CLASS(&a->intcioexp[i]);
> > + /* INTC_IOEXP internal: orgate[i] -> input[i] */
> > + for (int j = 0; j < icio->num_inpins; j++) {
> > + irq = qdev_get_gpio_in(DEVICE(&a->intcioexp[i]), j);
> > + qdev_connect_gpio_out(DEVICE(&a->intcioexp[i].orgates[j]),
> 0,
> > + irq);
> > + }
> > +
> > + /* INTC_IOEXP output[i] -> INTC0.orgate[0].input[i] */
> > + for (int j = 0; j < icio->num_outpins; j++) {
> > + irq = qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), j);
> > + sysbus_connect_irq(SYS_BUS_DEVICE(&a->intcioexp[i]), j,
> > + irq);
> > + }
> > }
> >
> > aspeed_mmio_map_unimplemented(s->memory,
> > SYS_BUS_DEVICE(&s->dpmcu), diff --git a/hw/intc/aspeed_intc.c
> > b/hw/intc/aspeed_intc.c index 5cd786dee6..a04005ee7c 100644
> > --- a/hw/intc/aspeed_intc.c
> > +++ b/hw/intc/aspeed_intc.c
> > @@ -924,6 +924,64 @@ static const TypeInfo aspeed_2700_intc_info = {
> > .class_init = aspeed_2700_intc_class_init,
> > };
> >
> > +static AspeedINTCIRQ
> aspeed_2700_intcioexp2_irqs[ASPEED_INTC_MAX_INPINS] = {
> > + {0, 8, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> > + {1, 9, 1, R_GICINT193_EN, R_GICINT193_STATUS}, };
> > +
> > +static void aspeed_2700_intcioexp2_class_init(ObjectClass *klass,
> > + const void *data)
> {
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
> > +
> > + dc->desc = "ASPEED 2700 IOEXP2 INTC Controller";
> > + aic->num_lines = 32;
> > + aic->num_inpins = 2;
> > + aic->num_outpins = 10;
> > + aic->mem_size = 0x400;
> > + aic->nr_regs = 0x58 >> 2;
> > + aic->reg_offset = 0x100;
> > + aic->reg_ops = &aspeed_intcio_ops;
> > + aic->irq_table = aspeed_2700_intcioexp2_irqs;
> > + aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcioexp2_irqs);
> > +}
> > +
> > +static const TypeInfo aspeed_2700_intcioexp2_info = {
> > + .name = TYPE_ASPEED_2700_INTCIOEXP2,
> > + .parent = TYPE_ASPEED_INTC,
> > + .class_init = aspeed_2700_intcioexp2_class_init,
> > +};
> > +
> > +static AspeedINTCIRQ
> aspeed_2700_intcioexp1_irqs[ASPEED_INTC_MAX_INPINS] = {
> > + {0, 6, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> > + {1, 7, 1, R_GICINT193_EN, R_GICINT193_STATUS}, };
> > +
> > +static void aspeed_2700_intcioexp1_class_init(ObjectClass *klass,
> > + const void *data)
> {
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
> > +
> > + dc->desc = "ASPEED 2700 IOEXP1 INTC Controller";
> > + aic->num_lines = 32;
> > + aic->num_inpins = 2;
> > + aic->num_outpins = 10;
> > + aic->mem_size = 0x400;
> > + aic->nr_regs = 0x58 >> 2;
> > + aic->reg_offset = 0x100;
> > + aic->reg_ops = &aspeed_intcio_ops;
> > + aic->irq_table = aspeed_2700_intcioexp1_irqs;
> > + aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcioexp1_irqs);
> > +}
> > +
> > +static const TypeInfo aspeed_2700_intcioexp1_info = {
> > + .name = TYPE_ASPEED_2700_INTCIOEXP1,
> > + .parent = TYPE_ASPEED_INTC,
> > + .class_init = aspeed_2700_intcioexp1_class_init,
> > +};
> > +
> > static AspeedINTCIRQ
> aspeed_2700_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
> > {0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> > {1, 1, 1, R_GICINT193_EN, R_GICINT193_STATUS}, @@ -1099,6
> > +1157,8 @@ static void aspeed_intc_register_types(void)
> > type_register_static(&aspeed_intc_info);
> > type_register_static(&aspeed_2700_intc_info);
> > type_register_static(&aspeed_2700_intcio_info);
> > + type_register_static(&aspeed_2700_intcioexp1_info);
> > + type_register_static(&aspeed_2700_intcioexp2_info);
> > type_register_static(&aspeed_2700ssp_intc_info);
> > type_register_static(&aspeed_2700ssp_intcio_info);
> > type_register_static(&aspeed_2700tsp_intc_info);
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-12-26 1:34 ` Kane Chen
@ 2025-12-27 17:50 ` Cédric Le Goater
2025-12-29 10:00 ` Kane Chen
0 siblings, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2025-12-27 17:50 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, nabihestefan@google.com
Hello Kane,
> Thank you for the suggestion. Since I need to submit a v5 patch to split the I2C
> code changes anyway,
Can you please introduce the bus label property at the end of the
patch series ? Please consider adding a functional test and updating
the documentation too.
> I will handle the naming adjustments and other minor fixes
> myself in that version.
Thanks,
C.
^ permalink raw reply [flat|nested] 74+ messages in thread
* RE: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-12-27 17:50 ` Cédric Le Goater
@ 2025-12-29 10:00 ` Kane Chen
2025-12-29 11:41 ` Cédric Le Goater
0 siblings, 1 reply; 74+ messages in thread
From: Kane Chen @ 2025-12-29 10:00 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, nabihestefan@google.com
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Sunday, December 28, 2025 1:51 AM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; nabihestefan@google.com
> Subject: Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller
> for AST1700
>
> Hello Kane,
>
> > Thank you for the suggestion. Since I need to submit a v5 patch to
> > split the I2C code changes anyway,
>
> Can you please introduce the bus label property at the end of the patch series ?
> Please consider adding a functional test and updating the documentation too.
>
> > I will handle the naming adjustments and other minor fixes myself in
> > that version.
>
> Thanks,
>
> C.
Hi Cédric,
If I move the bus label property to the end of this patch series, it will trigger
a test failure in the current patch series. To avoid this, I plan to move the bus
label changes into a separate patch series and submit it before the AST1700
series. I believe this approach ensures both series pass the tests properly.
What are your thoughts on this?
Best Regards,
Kane
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-12-29 10:00 ` Kane Chen
@ 2025-12-29 11:41 ` Cédric Le Goater
2025-12-29 16:51 ` Cédric Le Goater
0 siblings, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2025-12-29 11:41 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, nabihestefan@google.com
On 12/29/25 11:00, Kane Chen wrote:
>> -----Original Message-----
>> From: Cédric Le Goater <clg@kaod.org>
>> Sent: Sunday, December 28, 2025 1:51 AM
>> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
>> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
>> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
>> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
>> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
>> here <qemu-devel@nongnu.org>
>> Cc: Troy Lee <troy_lee@aspeedtech.com>; nabihestefan@google.com
>> Subject: Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller
>> for AST1700
>>
>> Hello Kane,
>>
>>> Thank you for the suggestion. Since I need to submit a v5 patch to
>>> split the I2C code changes anyway,
>>
>> Can you please introduce the bus label property at the end of the patch series ?
>> Please consider adding a functional test and updating the documentation too.
>>
>>> I will handle the naming adjustments and other minor fixes myself in
>>> that version.
>>
>> Thanks,
>>
>> C.
>
> Hi Cédric,
>
> If I move the bus label property to the end of this patch series, it will trigger
> a test failure in the current patch series.
Which test ?
> To avoid this, I plan to move the bus
> label changes into a separate patch series and submit it before the AST1700
> series. I believe this approach ensures both series pass the tests properly.
> What are your thoughts on this?
I would like to understand the issue first.
Thanks,
C.
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-12-29 11:41 ` Cédric Le Goater
@ 2025-12-29 16:51 ` Cédric Le Goater
2025-12-29 19:35 ` Nabih Estefan
0 siblings, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2025-12-29 16:51 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, nabihestefan@google.com,
'Philippe Mathieu-Daudé'
+phil
On 12/29/25 12:41, Cédric Le Goater wrote:
> On 12/29/25 11:00, Kane Chen wrote:
>>> -----Original Message-----
>>> From: Cédric Le Goater <clg@kaod.org>
>>> Sent: Sunday, December 28, 2025 1:51 AM
>>> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
>>> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
>>> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
>>> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
>>> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
>>> here <qemu-devel@nongnu.org>
>>> Cc: Troy Lee <troy_lee@aspeedtech.com>; nabihestefan@google.com
>>> Subject: Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller
>>> for AST1700
>>>
>>> Hello Kane,
>>>
>>>> Thank you for the suggestion. Since I need to submit a v5 patch to
>>>> split the I2C code changes anyway,
>>>
>>> Can you please introduce the bus label property at the end of the patch series ?
>>> Please consider adding a functional test and updating the documentation too.
>>>
>>>> I will handle the naming adjustments and other minor fixes myself in
>>>> that version.
>>>
>>> Thanks,
>>>
>>> C.
>>
>> Hi Cédric,
>>
>> If I move the bus label property to the end of this patch series, it will trigger
>> a test failure in the current patch series.
>
> Which test ?
>
>> To avoid this, I plan to move the bus
>> label changes into a separate patch series and submit it before the AST1700
>> series. I believe this approach ensures both series pass the tests properly.
>> What are your thoughts on this?
>
> I would like to understand the issue first.
I see.
The AST2700 functional tests fail :
self.vm.add_args('-device',
'tmp105,bus=aspeed.i2c.bus.1,address=0x4d,id=tmp-test')
The "bus label" proposal renames the IO expander I2C buses (32) to avoid
the name conflicts :
/aspeed.ioexp0.i2c.bus.0 (i2c-bus)
...
/aspeed.ioexp0.i2c.bus.15 (i2c-bus)
/aspeed.ioexp1.i2c.bus.0 (i2c-bus)
...
/aspeed.ioexp1.i2c.bus.15 (i2c-bus)
Since this will be exposed in the user API, it would be best to avoid
introducing poorly chosen names. Having so many I2C buses (48) in a
single machine is somewhat new in QEMU and I am not aware of any naming
convention for this.
May be others do ?
Thanks,
C.
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-12-29 16:51 ` Cédric Le Goater
@ 2025-12-29 19:35 ` Nabih Estefan
2025-12-30 9:58 ` Kane Chen
0 siblings, 1 reply; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:35 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Troy Lee,
Philippe Mathieu-Daudé
On Mon, Dec 29, 2025 at 8:51 AM Cédric Le Goater <clg@kaod.org> wrote:
>
> +phil
>
> On 12/29/25 12:41, Cédric Le Goater wrote:
> > On 12/29/25 11:00, Kane Chen wrote:
> >>> -----Original Message-----
> >>> From: Cédric Le Goater <clg@kaod.org>
> >>> Sent: Sunday, December 28, 2025 1:51 AM
> >>> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> >>> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> >>> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> >>> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> >>> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> >>> here <qemu-devel@nongnu.org>
> >>> Cc: Troy Lee <troy_lee@aspeedtech.com>; nabihestefan@google.com
> >>> Subject: Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller
> >>> for AST1700
> >>>
> >>> Hello Kane,
> >>>
> >>>> Thank you for the suggestion. Since I need to submit a v5 patch to
> >>>> split the I2C code changes anyway,
> >>>
> >>> Can you please introduce the bus label property at the end of the patch series ?
> >>> Please consider adding a functional test and updating the documentation too.
> >>>
> >>>> I will handle the naming adjustments and other minor fixes myself in
> >>>> that version.
> >>>
> >>> Thanks,
> >>>
> >>> C.
> >>
> >> Hi Cédric,
> >>
> >> If I move the bus label property to the end of this patch series, it will trigger
> >> a test failure in the current patch series.
> >
> > Which test ?
> >
> >> To avoid this, I plan to move the bus
> >> label changes into a separate patch series and submit it before the AST1700
> >> series. I believe this approach ensures both series pass the tests properly.
> >> What are your thoughts on this?
> >
> > I would like to understand the issue first.
> I see.
>
> The AST2700 functional tests fail :
>
> self.vm.add_args('-device',
> 'tmp105,bus=aspeed.i2c.bus.1,address=0x4d,id=tmp-test')
>
> The "bus label" proposal renames the IO expander I2C buses (32) to avoid
> the name conflicts :
>
> /aspeed.ioexp0.i2c.bus.0 (i2c-bus)
> ...
> /aspeed.ioexp0.i2c.bus.15 (i2c-bus)
>
> /aspeed.ioexp1.i2c.bus.0 (i2c-bus)
> ...
> /aspeed.ioexp1.i2c.bus.15 (i2c-bus)
>
> Since this will be exposed in the user API, it would be best to avoid
> introducing poorly chosen names. Having so many I2C buses (48) in a
> single machine is somewhat new in QEMU and I am not aware of any naming
> convention for this.
>
> May be others do ?
>
> Thanks,
>
> C.
I'm not aware of any convention, but I'd argue the current naming with
the bus label makes sense. A i2c bus on the main machine is
"aspeed.i2c.bus.%d" which clearly makes it easy to differenciate but
see that the two busses are somehow related. Maybe it'd be worth
changing the `aspeed_i2c_class_init` to make this relation more
obvious by not using TYPE_ASPEED_I2C_BUS but use the string
explicitly?
Thanks,
Nabih
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (18 preceding siblings ...)
2025-12-24 1:41 ` [PATCH v4 19/19] hw/arm/aspeed: Enable AST1700 IO expander support Kane Chen via
@ 2025-12-29 19:37 ` Nabih Estefan
2026-01-19 7:45 ` Cédric Le Goater
20 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:37 UTC (permalink / raw)
To: Kane Chen
Cc: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee
On Tue, Dec 23, 2025 at 5:42 PM Kane Chen <kane_chen@aspeedtech.com> wrote:
>
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Hi all,
>
> LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP DC-SCM
> 2.0 specification (see Figure 2):
> https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
>
> LTPI provides a protocol and physical interface for tunneling various
> low-speed signals between the Host Processor Module (HPM) and the
> Satellite Controller Module (SCM). In Figure 2 of the specification,
> the AST27x0 SoC (left) integrates two LTPI controllers, allowing it to
> connect to up to two AST1700 boards. On the other side, the AST1700
> consolidates HPM FPGA functions and multiple peripheral interfaces
> (GPIO, UART, I2C, I3C, etc.) onto a single board.
>
> Because the AST1700 exposes additional I/O interfaces (GPIO, I2C, I3C,
> and others), it acts as an I/O expander. Once connected over LTPI,
> the AST27x0 can control additional downstream devices through this link.
>
> This patch series is based on the SGPIO changes:
> https://patchwork.kernel.org/project/qemu-devel/patch/20251219-aspeed-sgpio-v5-1-fd5593178144@google.com/
>
> It introduces a basic LTPI controller model and wires it into the
> AST27x0 SoC. The series also adds the AST1700-specific LTPI expander
> device and incrementally connects common peripherals on the AST1700
> model. For the I3C block, which may cause kernel crashes, its MMIO
> region is modeled as an unimplemented device to reserve address space
> and make the missing functionality explicit, ensuring stable guest
> probing.
>
> In the official release images, the AST1700 functions are not included
> by default. To test the AST1700-related functionality, please include
> the following DTS files for probing:
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-ltpi0.dtsi
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-ltpi1.dtsi
>
> After including these DTS files in the BMC image, you can verify LTPI
> functionality using the following scenarios:
>
> 1. In U-Boot:
> Run the ltpi command to trigger the LTPI connection and display the
> current connection status.
> 2. In BMC Linux:
> Run i2cdetect -y <16-38> to scan and test the I2C buses exposed by
> the AST1700.
>
> Any feedback or suggestions are appreciated!
>
> Kane
>
Adding the explanation of the tested tag in every patch feels
unnecessary since the tests applied equally to all patches. However, I
didn't want to add the tag without any explanation, so I figured I
might as well reply to the cover letter. I tested between patches to
make sure all our internal tests passed and there was no unexpected
breakages, and once the whole patchset landed tested against our
internal ast2700 machines and was able to see the i2c buses and attach
devices to them.
> ---
>
> ChangeLog
> ---------
> v4:
> - Add missing Signed-off-by
> - Fix checkpatch.pl warnings
> - Refine code structure
> - Enable AST1700 support only after all devices are ready
>
> v3:
> - Add PWM model
> - Integrate the SGPIO model
> - Fix I2C test case failure
> - Refine code structure
>
> v2:
> - Separate the AST1700 model into a standalone implementation
> - Refine the mechanism for assigning the AST1700 board number
>
> v1:
> - Initial version
> ---
>
> Kane-Chen-AS (19):
> hw/misc: Add LTPI controller
> hw/arm/aspeed: Attach LTPI controller to AST27X0 platform
> hw/misc: Add basic Aspeed PWM model
> hw/arm/aspeed: Add AST1700 LTPI expander device model
> hw/arm/aspeed: Integrate AST1700 device into AST27X0
> hw/arm/aspeed: Integrate interrupt controller for AST1700
> hw/arm/aspeed: Attach LTPI controller to AST1700 model
> hw/arm/aspeed: Attach UART device to AST1700 model
> hw/arm/aspeed: Attach SRAM device to AST1700 model
> hw/arm/aspeed: Attach SPI device to AST1700 model
> hw/arm/aspeed: Attach ADC device to AST1700 model
> hw/arm/aspeed: Attach SCU device to AST1700 model
> hw/arm/aspeed: Attach GPIO device to AST1700 model
> hw/arm/aspeed: attach I2C device to AST1700 model
> hw/arm/aspeed: Attach WDT device to AST1700 model
> hw/arm/aspeed: Attach PWM device to AST1700 model
> hw/arm/aspeed: Attach SGPIOM device to AST1700 model
> hw/arm/aspeed: Model AST1700 I3C block as unimplemented device
> hw/arm/aspeed: Enable AST1700 IO expander support
>
> include/hw/arm/aspeed_ast1700.h | 53 +++++++
> include/hw/arm/aspeed_soc.h | 25 ++-
> include/hw/i2c/aspeed_i2c.h | 1 +
> include/hw/intc/aspeed_intc.h | 2 +
> include/hw/misc/aspeed_ltpi.h | 33 ++++
> include/hw/misc/aspeed_pwm.h | 31 ++++
> hw/arm/aspeed_ast1700.c | 268 ++++++++++++++++++++++++++++++++
> hw/arm/aspeed_ast27x0.c | 165 ++++++++++++++++++--
> hw/i2c/aspeed_i2c.c | 19 ++-
> hw/intc/aspeed_intc.c | 60 +++++++
> hw/misc/aspeed_ltpi.c | 193 +++++++++++++++++++++++
> hw/misc/aspeed_pwm.c | 121 ++++++++++++++
> hw/arm/meson.build | 1 +
> hw/misc/meson.build | 2 +
> hw/misc/trace-events | 4 +
> 15 files changed, 959 insertions(+), 19 deletions(-)
> create mode 100644 include/hw/arm/aspeed_ast1700.h
> create mode 100644 include/hw/misc/aspeed_ltpi.h
> create mode 100644 include/hw/misc/aspeed_pwm.h
> create mode 100644 hw/arm/aspeed_ast1700.c
> create mode 100644 hw/misc/aspeed_ltpi.c
> create mode 100644 hw/misc/aspeed_pwm.c
>
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 01/19] hw/misc: Add LTPI controller
2025-12-24 10:36 ` Cédric Le Goater
@ 2025-12-29 19:37 ` Nabih Estefan
0 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:37 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee
On Wed, Dec 24, 2025 at 2:36 AM Cédric Le Goater <clg@kaod.org> wrote:
>
> On 12/24/25 02:41, Kane Chen via wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP DC-SCM
> > 2.0 specification:
> > https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
> >
> > LTPI is a protocol and physical interface for tunneling various low-speed
> > signals between the HPM and SCM. As shown in Figure 2, the AST27x0 (left)
> > integrates two LTPI controllers, allowing it to connect to up to two
> > extended boards.
> >
> > This commit introduces a simple device model for the ASPEED LTPI
> > controller in QEMU.
> >
> > The model includes basic MMIO read/write operations and sets default
> > register values during reset to emulate a link-up state.
> >
> > Implements register space with read/write callbacks.
> >
> > Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
> > ---
> > include/hw/misc/aspeed_ltpi.h | 33 ++++++
> > hw/misc/aspeed_ltpi.c | 193 ++++++++++++++++++++++++++++++++++
> > hw/misc/meson.build | 1 +
> > 3 files changed, 227 insertions(+)
> > create mode 100644 include/hw/misc/aspeed_ltpi.h
> > create mode 100644 hw/misc/aspeed_ltpi.c
> >
> > diff --git a/include/hw/misc/aspeed_ltpi.h b/include/hw/misc/aspeed_ltpi.h
> > new file mode 100644
> > index 0000000000..e991afc666
> > --- /dev/null
> > +++ b/include/hw/misc/aspeed_ltpi.h
> > @@ -0,0 +1,33 @@
> > +/*
> > + * ASPEED LTPI Controller
> > + *
> > + * Copyright (C) 2025 ASPEED Technology Inc.
> > + *
> > + * SPDX-License-Identifier: GPL-2.0-or-later
> > + */
> > +#ifndef ASPEED_LTPI_H
> > +#define ASPEED_LTPI_H
> > +
> > +#include "hw/sysbus.h"
> > +
> > +#define TYPE_ASPEED_LTPI "aspeed.ltpi-ctrl"
> > +OBJECT_DECLARE_SIMPLE_TYPE(AspeedLTPIState, ASPEED_LTPI)
> > +
> > +#define ASPEED_LTPI_TOTAL_SIZE 0x900
> > +#define ASPEED_LTPI_CTRL_SIZE 0x200
> > +#define ASPEED_LTPI_PHY_SIZE 0x100
> > +#define ASPEED_LTPI_TOP_SIZE 0x100
> > +
> > +struct AspeedLTPIState {
> > + SysBusDevice parent;
> > + MemoryRegion mmio;
> > + MemoryRegion mmio_ctrl;
> > + MemoryRegion mmio_phy;
> > + MemoryRegion mmio_top;
> > +
> > + uint32_t ctrl_regs[ASPEED_LTPI_CTRL_SIZE >> 2];
> > + uint32_t phy_regs[ASPEED_LTPI_PHY_SIZE >> 2];
> > + uint32_t top_regs[ASPEED_LTPI_TOP_SIZE >> 2];
> > +};
> > +
> > +#endif /* ASPEED_LTPI_H */
> > diff --git a/hw/misc/aspeed_ltpi.c b/hw/misc/aspeed_ltpi.c
> > new file mode 100644
> > index 0000000000..131cea9c6b
> > --- /dev/null
> > +++ b/hw/misc/aspeed_ltpi.c
> > @@ -0,0 +1,193 @@
> > +/*
> > + * ASPEED LTPI Controller
> > + *
> > + * Copyright (C) 2025 ASPEED Technology Inc.
> > + *
> > + * SPDX-License-Identifier: GPL-2.0-or-later
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu/log.h"
> > +#include "migration/vmstate.h"
> > +#include "hw/misc/aspeed_ltpi.h"
> > +
> > +#define ASPEED_LTPI_CTRL_BASE 0x000
> > +#define ASPEED_LTPI_PHY_BASE 0x200
> > +#define ASPEED_LTPI_TOP_BASE 0x800
> > +
> > +#define LTPI_CTRL_LINK_MNG 0x42
> > +#define LTPI_PHY_MODE 0x0
> > +
> > +static uint64_t aspeed_ltpi_top_read(void *opaque, hwaddr offset, unsigned size)
> > +{
> > + AspeedLTPIState *s = opaque;
> > + uint32_t idx = offset >> 2;
> > +
> > + return s->top_regs[idx];
> > +}
> > +
> > +static void aspeed_ltpi_top_write(void *opaque, hwaddr offset,
> > + uint64_t val, unsigned size)
> > +{
> > + AspeedLTPIState *s = opaque;
> > + uint32_t idx = offset >> 2;
> > +
> > + switch (offset) {
> > + default:
> > + s->top_regs[idx] = (uint32_t)val;
> > + break;
> > + }
> > +}
> > +
> > +static const MemoryRegionOps aspeed_ltpi_top_ops = {
> > + .read = aspeed_ltpi_top_read,
> > + .write = aspeed_ltpi_top_write,
> > + .endianness = DEVICE_LITTLE_ENDIAN,
> > + .valid = {
> > + .min_access_size = 1,
> > + .max_access_size = 4,
> > + },
> > +};
> > +
> > +static uint64_t aspeed_ltpi_phy_read(void *opaque, hwaddr offset, unsigned size)
> > +{
> > + AspeedLTPIState *s = opaque;
> > + uint32_t idx = offset >> 2;
> > +
> > + return s->phy_regs[idx];
> > +}
> > +
> > +static void aspeed_ltpi_phy_write(void *opaque, hwaddr offset,
> > + uint64_t val, unsigned size)
> > +{
> > + AspeedLTPIState *s = opaque;
> > + uint32_t idx = offset >> 2;
> > +
> > + switch (offset) {
> > + default:
> > + s->phy_regs[idx] = (uint32_t)val;
> > + break;
> > + }
> > +}
> > +
> > +static const MemoryRegionOps aspeed_ltpi_phy_ops = {
> > + .read = aspeed_ltpi_phy_read,
> > + .write = aspeed_ltpi_phy_write,
> > + .endianness = DEVICE_LITTLE_ENDIAN,
> > + .valid = {
> > + .min_access_size = 1,
> > + .max_access_size = 4,
> > + },
> > +};
> > +
> > +static uint64_t aspeed_ltpi_ctrl_read(void *opaque,
> > + hwaddr offset, unsigned size)
> > +{
> > + AspeedLTPIState *s = opaque;
> > + uint32_t idx = offset >> 2;
> > +
> > + return s->ctrl_regs[idx];
> > +}
> > +
> > +static void aspeed_ltpi_ctrl_write(void *opaque, hwaddr offset,
> > + uint64_t val, unsigned size)
> > +{
> > + AspeedLTPIState *s = opaque;
> > + uint32_t idx = offset >> 2;
> > +
> > + switch (offset) {
> > + default:
> > + s->ctrl_regs[idx] = (uint32_t)val;
> > + break;
> > + }
> > +}
> > +
> > +static const MemoryRegionOps aspeed_ltpi_ctrl_ops = {
> > + .read = aspeed_ltpi_ctrl_read,
> > + .write = aspeed_ltpi_ctrl_write,
> > + .endianness = DEVICE_LITTLE_ENDIAN,
> > + .valid = {
> > + .min_access_size = 1,
> > + .max_access_size = 4,
> > + },
> > +};
> > +
> > +static void aspeed_ltpi_reset(DeviceState *dev)
> > +{
> > + AspeedLTPIState *s = ASPEED_LTPI(dev);
> > +
> > + memset(s->ctrl_regs, 0, sizeof(s->ctrl_regs));
> > + memset(s->phy_regs, 0, sizeof(s->phy_regs));
> > + memset(s->top_regs, 0, sizeof(s->top_regs));
> > + /* set default values */
> > + s->ctrl_regs[LTPI_CTRL_LINK_MNG] = 0x11900007;
> > + s->phy_regs[LTPI_PHY_MODE] = 0x2;
> > +}
> > +
> > +
> > +static const VMStateDescription vmstate_aspeed_ltpi = {
> > + .name = TYPE_ASPEED_LTPI,
> > + .version_id = 1,
> > + .minimum_version_id = 1,
> > + .fields = (VMStateField[]) {
> > + VMSTATE_UINT32_ARRAY(ctrl_regs, AspeedLTPIState,
> > + ASPEED_LTPI_CTRL_SIZE >> 2),
> > + VMSTATE_UINT32_ARRAY(phy_regs, AspeedLTPIState,
> > + ASPEED_LTPI_PHY_SIZE >> 2),
> > + VMSTATE_UINT32_ARRAY(top_regs, AspeedLTPIState,
> > + ASPEED_LTPI_TOP_SIZE >> 2),
> > +
> > + VMSTATE_END_OF_LIST()
> > + }
> > +};
> > +
> > +static void aspeed_ltpi_realize(DeviceState *dev, Error **errp)
> > +{
> > + AspeedLTPIState *s = ASPEED_LTPI(dev);
> > +
> > + memory_region_init(&s->mmio, OBJECT(s), TYPE_ASPEED_LTPI,
> > + ASPEED_LTPI_TOTAL_SIZE);
> > +
> > + memory_region_init_io(&s->mmio_ctrl, OBJECT(s),
> > + &aspeed_ltpi_ctrl_ops, s,
> > + "aspeed-ltpi-ctrl", ASPEED_LTPI_CTRL_SIZE);
> > +
> > + memory_region_init_io(&s->mmio_phy, OBJECT(s),
> > + &aspeed_ltpi_phy_ops, s,
> > + "aspeed-ltpi-phy", ASPEED_LTPI_PHY_SIZE);
> > +
> > + memory_region_init_io(&s->mmio_top, OBJECT(s),
> > + &aspeed_ltpi_top_ops, s,
> > + "aspeed-ltpi-top", ASPEED_LTPI_TOP_SIZE);
> > +
> > + memory_region_add_subregion(&s->mmio,
> > + ASPEED_LTPI_CTRL_BASE, &s->mmio_ctrl);
> > + memory_region_add_subregion(&s->mmio,
> > + ASPEED_LTPI_PHY_BASE, &s->mmio_phy);
> > + memory_region_add_subregion(&s->mmio,
> > + ASPEED_LTPI_TOP_BASE, &s->mmio_top);
> > +
> > + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
> > +}
> > +
> > +static void aspeed_ltpi_class_init(ObjectClass *klass, const void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + dc->realize = aspeed_ltpi_realize;
> > + dc->vmsd = &vmstate_aspeed_ltpi;
> > + device_class_set_legacy_reset(dc, aspeed_ltpi_reset);
> > +}
> > +
> > +static const TypeInfo aspeed_ltpi_info = {
> > + .name = TYPE_ASPEED_LTPI,
> > + .parent = TYPE_SYS_BUS_DEVICE,
> > + .instance_size = sizeof(AspeedLTPIState),
> > + .class_init = aspeed_ltpi_class_init,
> > +};
> > +
> > +static void aspeed_ltpi_register_types(void)
> > +{
> > + type_register_static(&aspeed_ltpi_info);
> > +}
> > +
> > +type_init(aspeed_ltpi_register_types);
> > diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> > index b1d8d8e5d2..45b16e7797 100644
> > --- a/hw/misc/meson.build
> > +++ b/hw/misc/meson.build
> > @@ -136,6 +136,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> > 'aspeed_hace.c',
> > 'aspeed_i3c.c',
> > 'aspeed_lpc.c',
> > + 'aspeed_ltpi.c',
> > 'aspeed_scu.c',
> > 'aspeed_sbc.c',
> > 'aspeed_sdmc.c',
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 02/19] hw/arm/aspeed: Attach LTPI controller to AST27X0 platform
2025-12-24 1:41 ` [PATCH v4 02/19] hw/arm/aspeed: Attach LTPI controller to AST27X0 platform Kane Chen via
@ 2025-12-29 19:37 ` Nabih Estefan
0 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:37 UTC (permalink / raw)
To: Kane Chen
Cc: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee, Cédric Le Goater
On Tue, Dec 23, 2025 at 5:42 PM Kane Chen <kane_chen@aspeedtech.com> wrote:
>
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the LTPI controller device (representing the AST1700 I/O
> expander) to the AST27X0 SoC model. This patch sets up the memory
> mapping and device registration according to the AST2700 SoC design,
> where the LTPI controller is exposed at fixed MMIO regions.
>
> This change only handles device instantiation and integration,
> without implementing the controller's internal logic.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
> ---
> include/hw/arm/aspeed_soc.h | 5 +++++
> hw/arm/aspeed_ast27x0.c | 21 +++++++++++++++++++++
> 2 files changed, 26 insertions(+)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 18ff961a38..bca10c387b 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -43,6 +43,7 @@
> #include "hw/fsi/aspeed_apb2opb.h"
> #include "hw/char/serial-mm.h"
> #include "hw/intc/arm_gicv3.h"
> +#include "hw/misc/aspeed_ltpi.h"
>
> #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
>
> @@ -55,6 +56,7 @@
> #define ASPEED_UARTS_NUM 13
> #define ASPEED_JTAG_NUM 2
> #define ASPEED_PCIE_NUM 3
> +#define ASPEED_IOEXP_NUM 2
>
> struct AspeedSoCState {
> DeviceState parent;
> @@ -112,6 +114,7 @@ struct AspeedSoCState {
> UnimplementedDeviceState ltpi;
> UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
> AspeedAPB2OPBState fsi[2];
> + AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM];
> };
>
> #define TYPE_ASPEED_SOC "aspeed-soc"
> @@ -279,6 +282,8 @@ enum {
> ASPEED_GIC_REDIST,
> ASPEED_DEV_IPC0,
> ASPEED_DEV_IPC1,
> + ASPEED_DEV_LTPI_CTRL1,
> + ASPEED_DEV_LTPI_CTRL2,
> };
>
> const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 70be3871bb..341b53189b 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -88,6 +88,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_UART10] = 0x14C33900,
> [ASPEED_DEV_UART11] = 0x14C33A00,
> [ASPEED_DEV_UART12] = 0x14C33B00,
> + [ASPEED_DEV_LTPI_CTRL1] = 0x14C34000,
> + [ASPEED_DEV_LTPI_CTRL2] = 0x14C35000,
> [ASPEED_DEV_WDT] = 0x14C37000,
> [ASPEED_DEV_LTPI] = 0x30000000,
> [ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
> @@ -556,6 +558,11 @@ static void aspeed_soc_ast2700_init(Object *obj)
> object_property_set_int(OBJECT(&s->pcie[i]), "id", i, &error_abort);
> }
>
> + for (i = 0; i < ASPEED_IOEXP_NUM; i++) {
> + object_initialize_child(obj, "ltpi-ctrl[*]",
> + &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI);
> + }
> +
> object_initialize_child(obj, "dpmcu", &s->dpmcu,
> TYPE_UNIMPLEMENTED_DEVICE);
> object_initialize_child(obj, "ltpi", &s->ltpi,
> @@ -1047,6 +1054,20 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> return;
> }
>
> + /* LTPI controller */
> + for (i = 0; i < ASPEED_IOEXP_NUM; i++) {
> + AspeedLTPIState *ltpi_ctrl;
> + hwaddr ltpi_base;
> +
> + ltpi_ctrl = ASPEED_LTPI(&s->ltpi_ctrl[i]);
> + ltpi_base = sc->memmap[ASPEED_DEV_LTPI_CTRL1 + i];
> +
> + if (!sysbus_realize(SYS_BUS_DEVICE(ltpi_ctrl), errp)) {
> + return;
> + }
> + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base);
> + }
> +
> aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
> "aspeed.dpmcu",
> sc->memmap[ASPEED_DEV_DPMCU],
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 03/19] hw/misc: Add basic Aspeed PWM model
2025-12-24 10:37 ` Cédric Le Goater
@ 2025-12-29 19:37 ` Nabih Estefan
0 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:37 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee
On Wed, Dec 24, 2025 at 2:37 AM Cédric Le Goater <clg@kaod.org> wrote:
>
> On 12/24/25 02:41, Kane Chen via wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> It should be From: clg ...
>
> I will fix it. Don't resend for that.
>
>
> Thanks,
>
> C.
>
> >
> > Add an initial PWM model for Aspeed SoCs, including device state,
> > register definitions, and basic initialization as a sysbus device.
> >
> > Signed-off-by: Cédric Le Goater <clg@kaod.org>
> > Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
> > ---
> > include/hw/arm/aspeed_soc.h | 3 +-
> > include/hw/misc/aspeed_pwm.h | 31 +++++++++
> > hw/misc/aspeed_pwm.c | 121 +++++++++++++++++++++++++++++++++++
> > hw/misc/meson.build | 1 +
> > hw/misc/trace-events | 4 ++
> > 5 files changed, 159 insertions(+), 1 deletion(-)
> > create mode 100644 include/hw/misc/aspeed_pwm.h
> > create mode 100644 hw/misc/aspeed_pwm.c
> >
> > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> > index bca10c387b..7b08cca908 100644
> > --- a/include/hw/arm/aspeed_soc.h
> > +++ b/include/hw/arm/aspeed_soc.h
> > @@ -28,6 +28,7 @@
> > #include "hw/misc/aspeed_hace.h"
> > #include "hw/misc/aspeed_sbc.h"
> > #include "hw/misc/aspeed_sli.h"
> > +#include "hw/misc/aspeed_pwm.h"
> > #include "hw/watchdog/wdt_aspeed.h"
> > #include "hw/net/ftgmac100.h"
> > #include "target/arm/cpu.h"
> > @@ -88,6 +89,7 @@ struct AspeedSoCState {
> > MemoryRegion secsram;
> > UnimplementedDeviceState sbc_unimplemented;
> > AspeedSDMCState sdmc;
> > + AspeedPWMState pwm;
> > AspeedWDTState wdt[ASPEED_WDTS_NUM];
> > FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
> > AspeedMiiState mii[ASPEED_MACS_NUM];
> > @@ -108,7 +110,6 @@ struct AspeedSoCState {
> > UnimplementedDeviceState video;
> > UnimplementedDeviceState emmc_boot_controller;
> > UnimplementedDeviceState dpmcu;
> > - UnimplementedDeviceState pwm;
> > UnimplementedDeviceState espi;
> > UnimplementedDeviceState udc;
> > UnimplementedDeviceState ltpi;
> > diff --git a/include/hw/misc/aspeed_pwm.h b/include/hw/misc/aspeed_pwm.h
> > new file mode 100644
> > index 0000000000..13dc3ea45b
> > --- /dev/null
> > +++ b/include/hw/misc/aspeed_pwm.h
> > @@ -0,0 +1,31 @@
> > +/*
> > + * ASPEED PWM Controller
> > + *
> > + * Copyright (C) 2017-2021 IBM Corp.
> > + *
> > + * This code is licensed under the GPL version 2 or later. See
> > + * the COPYING file in the top-level directory.
> > + */
> > +
> > +#ifndef ASPEED_PWM_H
> > +#define ASPEED_PWM_H
> > +
> > +#include "hw/sysbus.h"
> > +
> > +#define TYPE_ASPEED_PWM "aspeed.pwm"
> > +#define ASPEED_PWM(obj) OBJECT_CHECK(AspeedPWMState, (obj), TYPE_ASPEED_PWM)
> > +
> > +#define ASPEED_PWM_NR_REGS (0x10C >> 2)
> > +
> > +typedef struct AspeedPWMState {
> > + /* <private> */
> > + SysBusDevice parent;
> > +
> > + /*< public >*/
> > + MemoryRegion iomem;
> > + qemu_irq irq;
> > +
> > + uint32_t regs[ASPEED_PWM_NR_REGS];
> > +} AspeedPWMState;
> > +
> > +#endif /* _ASPEED_PWM_H_ */
> > diff --git a/hw/misc/aspeed_pwm.c b/hw/misc/aspeed_pwm.c
> > new file mode 100644
> > index 0000000000..de209274af
> > --- /dev/null
> > +++ b/hw/misc/aspeed_pwm.c
> > @@ -0,0 +1,121 @@
> > +/*
> > + * ASPEED PWM Controller
> > + *
> > + * Copyright (C) 2017-2021 IBM Corp.
> > + *
> > + * This code is licensed under the GPL version 2 or later. See
> > + * the COPYING file in the top-level directory.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu/log.h"
> > +#include "qemu/error-report.h"
> > +#include "hw/misc/aspeed_pwm.h"
> > +#include "qapi/error.h"
> > +#include "migration/vmstate.h"
> > +
> > +#include "trace.h"
> > +
> > +static uint64_t aspeed_pwm_read(void *opaque, hwaddr addr,
> > + unsigned int size)
> > +{
> > + AspeedPWMState *s = ASPEED_PWM(opaque);
> > + uint64_t val = 0;
> > +
> > + addr >>= 2;
> > +
> > + if (addr >= ASPEED_PWM_NR_REGS) {
> > + qemu_log_mask(LOG_GUEST_ERROR,
> > + "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
> > + __func__, addr << 2);
> > + } else {
> > + val = s->regs[addr];
> > + }
> > +
> > + trace_aspeed_pwm_read(addr << 2, val);
> > +
> > + return val;
> > +}
> > +
> > +static void aspeed_pwm_write(void *opaque, hwaddr addr, uint64_t data,
> > + unsigned int size)
> > +{
> > + AspeedPWMState *s = ASPEED_PWM(opaque);
> > +
> > + trace_aspeed_pwm_write(addr, data);
> > +
> > + addr >>= 2;
> > +
> > + if (addr >= ASPEED_PWM_NR_REGS) {
> > + qemu_log_mask(LOG_GUEST_ERROR,
> > + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
> > + __func__, addr << 2);
> > + return;
> > + }
> > +
> > + s->regs[addr] = data;
> > +}
> > +
> > +static const MemoryRegionOps aspeed_pwm_ops = {
> > + .read = aspeed_pwm_read,
> > + .write = aspeed_pwm_write,
> > + .endianness = DEVICE_LITTLE_ENDIAN,
> > + .valid = {
> > + .min_access_size = 1,
> > + .max_access_size = 4,
> > + },
> > +};
> > +
> > +static void aspeed_pwm_reset(DeviceState *dev)
> > +{
> > + struct AspeedPWMState *s = ASPEED_PWM(dev);
> > +
> > + memset(s->regs, 0, sizeof(s->regs));
> > +}
> > +
> > +static void aspeed_pwm_realize(DeviceState *dev, Error **errp)
> > +{
> > + AspeedPWMState *s = ASPEED_PWM(dev);
> > + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> > +
> > + sysbus_init_irq(sbd, &s->irq);
> > +
> > + memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_pwm_ops, s,
> > + TYPE_ASPEED_PWM, 0x1000);
> > +
> > + sysbus_init_mmio(sbd, &s->iomem);
> > +}
> > +
> > +static const VMStateDescription vmstate_aspeed_pwm = {
> > + .name = TYPE_ASPEED_PWM,
> > + .version_id = 1,
> > + .minimum_version_id = 1,
> > + .fields = (VMStateField[]) {
> > + VMSTATE_UINT32_ARRAY(regs, AspeedPWMState, ASPEED_PWM_NR_REGS),
> > + VMSTATE_END_OF_LIST(),
> > + }
> > +};
> > +
> > +static void aspeed_pwm_class_init(ObjectClass *klass, const void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > +
> > + dc->realize = aspeed_pwm_realize;
> > + device_class_set_legacy_reset(dc, aspeed_pwm_reset);
> > + dc->desc = "Aspeed PWM Controller";
> > + dc->vmsd = &vmstate_aspeed_pwm;
> > +}
> > +
> > +static const TypeInfo aspeed_pwm_info = {
> > + .name = TYPE_ASPEED_PWM,
> > + .parent = TYPE_SYS_BUS_DEVICE,
> > + .instance_size = sizeof(AspeedPWMState),
> > + .class_init = aspeed_pwm_class_init,
> > +};
> > +
> > +static void aspeed_pwm_register_types(void)
> > +{
> > + type_register_static(&aspeed_pwm_info);
> > +}
> > +
> > +type_init(aspeed_pwm_register_types);
> > diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> > index 45b16e7797..7afe1d0009 100644
> > --- a/hw/misc/meson.build
> > +++ b/hw/misc/meson.build
> > @@ -137,6 +137,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> > 'aspeed_i3c.c',
> > 'aspeed_lpc.c',
> > 'aspeed_ltpi.c',
> > + 'aspeed_pwm.c',
> > 'aspeed_scu.c',
> > 'aspeed_sbc.c',
> > 'aspeed_sdmc.c',
> > diff --git a/hw/misc/trace-events b/hw/misc/trace-events
> > index eeb9243898..f7870babba 100644
> > --- a/hw/misc/trace-events
> > +++ b/hw/misc/trace-events
> > @@ -299,6 +299,10 @@ aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64
> > aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64
> > aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
> >
> > +# aspeed_pwm.c
> > +aspeed_pwm_read(uint64_t offset, uint64_t data) "read: offset 0x%" PRIx64 " data 0x%" PRIx64
> > +aspeed_pwm_write(uint64_t offset, uint64_t data) "write: offset 0x%" PRIx64 " data 0x%" PRIx64
> > +
> > # aspeed_sdmc.c
> > aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
> > aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 04/19] hw/arm/aspeed: Add AST1700 LTPI expander device model
2025-12-24 1:41 ` [PATCH v4 04/19] hw/arm/aspeed: Add AST1700 LTPI expander device model Kane Chen via
2025-12-24 10:38 ` Cédric Le Goater
@ 2025-12-29 19:37 ` Nabih Estefan
1 sibling, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:37 UTC (permalink / raw)
To: Kane Chen
Cc: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee
On Tue, Dec 23, 2025 at 5:42 PM Kane Chen <kane_chen@aspeedtech.com> wrote:
>
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Introduce a minimal QEMU device model for the ASPEED AST1700, an
> MCU-less I/O expander used in the LTPI topology defined by the
> DC-SCM 2.0 specification (see figure 2):
> https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
>
> This initial implementation includes:
>
> * Definition of aspeed.ast1700 as a SysBusDevice
>
> * Setup of a basic memory region to reserve I/O space for future
> peripheral modeling
>
> This stub establishes the foundation for LTPI-related device emulation,
> without implementing any functional peripherals at this stage.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
> ---
> include/hw/arm/aspeed_ast1700.h | 23 ++++++++++++++++
> hw/arm/aspeed_ast1700.c | 47 +++++++++++++++++++++++++++++++++
> hw/arm/meson.build | 1 +
> 3 files changed, 71 insertions(+)
> create mode 100644 include/hw/arm/aspeed_ast1700.h
> create mode 100644 hw/arm/aspeed_ast1700.c
>
> diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
> new file mode 100644
> index 0000000000..2a95ebfe89
> --- /dev/null
> +++ b/include/hw/arm/aspeed_ast1700.h
> @@ -0,0 +1,23 @@
> +/*
> + * ASPEED AST1700 IO Expander
> + *
> + * Copyright (C) 2025 ASPEED Technology Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +#ifndef ASPEED_AST1700_H
> +#define ASPEED_AST1700_H
> +
> +#include "hw/sysbus.h"
> +
> +#define TYPE_ASPEED_AST1700 "aspeed.ast1700"
> +
> +OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700)
> +
> +struct AspeedAST1700SoCState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion iomem;
> +};
> +
> +#endif /* ASPEED_AST1700_H */
> diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
> new file mode 100644
> index 0000000000..bb6ca2ce9e
> --- /dev/null
> +++ b/hw/arm/aspeed_ast1700.c
> @@ -0,0 +1,47 @@
> +/*
> + * ASPEED AST1700 IO Expander
> + *
> + * Copyright (C) 2025 ASPEED Technology Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/boards.h"
> +#include "hw/qdev-core.h"
> +#include "qom/object.h"
> +#include "hw/arm/aspeed_ast1700.h"
> +
> +#define AST2700_SOC_LTPI_SIZE 0x01000000
> +
> +static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> +{
> + AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> +
> + /* Occupy memory space for all controllers in AST1700 */
> + memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700,
> + AST2700_SOC_LTPI_SIZE);
> + sysbus_init_mmio(sbd, &s->iomem);
> +}
> +
> +static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->realize = aspeed_ast1700_realize;
> +}
> +
> +static const TypeInfo aspeed_ast1700_info = {
> + .name = TYPE_ASPEED_AST1700,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(AspeedAST1700SoCState),
> + .class_init = aspeed_ast1700_class_init,
> +};
> +
> +static void aspeed_ast1700_register_types(void)
> +{
> + type_register_static(&aspeed_ast1700_info);
> +}
> +
> +type_init(aspeed_ast1700_register_types);
nit: missing trailing empty line.
> diff --git a/hw/arm/meson.build b/hw/arm/meson.build
> index aeaf654790..175942263d 100644
> --- a/hw/arm/meson.build
> +++ b/hw/arm/meson.build
> @@ -70,6 +70,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> 'aspeed_ast10x0_evb.c',
> 'fby35.c'))
> arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
> + 'aspeed_ast1700.c',
> 'aspeed_ast27x0.c',
> 'aspeed_ast27x0_evb.c',
> 'aspeed_ast27x0-fc.c',
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 05/19] hw/arm/aspeed: Integrate AST1700 device into AST27X0
2025-12-24 1:41 ` [PATCH v4 05/19] hw/arm/aspeed: Integrate AST1700 device into AST27X0 Kane Chen via
@ 2025-12-29 19:37 ` Nabih Estefan
0 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:37 UTC (permalink / raw)
To: Kane Chen
Cc: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee, Cédric Le Goater
On Tue, Dec 23, 2025 at 5:42 PM Kane Chen <kane_chen@aspeedtech.com> wrote:
>
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the AST1700 device as a child of the AST27X0 model to reflect
> its role in DC-SCM 2.0 LTPI-based architectures. This patch wires
> the AST1700 device into the platform without introducing functional
> peripherals.
>
> This forms the base for LTPI expander emulation in QEMU using
> AST27X0 as the host controller.
>
> Note: ioexp_num is set to 0 at this stage. Once all related devices
> and interrupts are fully implemented, ioexp_num will be updated to
> its expected value. This ensures the machine remains functional at
> every commit and avoids potential compiler or build issues.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
> ---
> include/hw/arm/aspeed_soc.h | 7 +++++--
> hw/arm/aspeed_ast27x0.c | 26 ++++++++++++++++++--------
> 2 files changed, 23 insertions(+), 10 deletions(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 7b08cca908..f19bab3457 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -45,6 +45,7 @@
> #include "hw/char/serial-mm.h"
> #include "hw/intc/arm_gicv3.h"
> #include "hw/misc/aspeed_ltpi.h"
> +#include "hw/arm/aspeed_ast1700.h"
>
> #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
>
> @@ -112,10 +113,10 @@ struct AspeedSoCState {
> UnimplementedDeviceState dpmcu;
> UnimplementedDeviceState espi;
> UnimplementedDeviceState udc;
> - UnimplementedDeviceState ltpi;
> UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
> AspeedAPB2OPBState fsi[2];
> AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM];
> + AspeedAST1700SoCState ioexp[ASPEED_IOEXP_NUM];
> };
>
> #define TYPE_ASPEED_SOC "aspeed-soc"
> @@ -178,6 +179,7 @@ struct AspeedSoCClass {
> int macs_num;
> int uarts_num;
> int uarts_base;
> + int ioexp_num;
> const int *irqmap;
> const hwaddr *memmap;
> uint32_t num_cpus;
> @@ -190,7 +192,6 @@ enum {
> ASPEED_DEV_IOMEM,
> ASPEED_DEV_IOMEM0,
> ASPEED_DEV_IOMEM1,
> - ASPEED_DEV_LTPI,
> ASPEED_DEV_UART0,
> ASPEED_DEV_UART1,
> ASPEED_DEV_UART2,
> @@ -285,6 +286,8 @@ enum {
> ASPEED_DEV_IPC1,
> ASPEED_DEV_LTPI_CTRL1,
> ASPEED_DEV_LTPI_CTRL2,
> + ASPEED_DEV_LTPI_IO0,
> + ASPEED_DEV_LTPI_IO1,
> };
>
> const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 341b53189b..de39a3e7eb 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -26,7 +26,6 @@
> #define AST2700_SOC_IO_SIZE 0x00FE0000
> #define AST2700_SOC_IOMEM_SIZE 0x01000000
> #define AST2700_SOC_DPMCU_SIZE 0x00040000
> -#define AST2700_SOC_LTPI_SIZE 0x01000000
>
> static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_VBOOTROM] = 0x00000000,
> @@ -91,7 +90,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_LTPI_CTRL1] = 0x14C34000,
> [ASPEED_DEV_LTPI_CTRL2] = 0x14C35000,
> [ASPEED_DEV_WDT] = 0x14C37000,
> - [ASPEED_DEV_LTPI] = 0x30000000,
> + [ASPEED_DEV_LTPI_IO0] = 0x30000000,
> + [ASPEED_DEV_LTPI_IO1] = 0x50000000,
> [ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
> [ASPEED_DEV_PCIE_MMIO1] = 0x80000000,
> [ASPEED_DEV_PCIE_MMIO2] = 0xA0000000,
> @@ -563,10 +563,14 @@ static void aspeed_soc_ast2700_init(Object *obj)
> &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI);
> }
>
> + for (i = 0; i < sc->ioexp_num; i++) {
> + /* AST1700 IOEXP */
> + object_initialize_child(obj, "ioexp[*]", &s->ioexp[i],
> + TYPE_ASPEED_AST1700);
> + }
> +
> object_initialize_child(obj, "dpmcu", &s->dpmcu,
> TYPE_UNIMPLEMENTED_DEVICE);
> - object_initialize_child(obj, "ltpi", &s->ltpi,
> - TYPE_UNIMPLEMENTED_DEVICE);
> object_initialize_child(obj, "iomem", &s->iomem,
> TYPE_UNIMPLEMENTED_DEVICE);
> object_initialize_child(obj, "iomem0", &s->iomem0,
> @@ -1068,14 +1072,19 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base);
> }
>
> + /* IO Expander */
> + for (i = 0; i < sc->ioexp_num; i++) {
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) {
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0,
> + sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
> + }
> +
> aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
> "aspeed.dpmcu",
> sc->memmap[ASPEED_DEV_DPMCU],
> AST2700_SOC_DPMCU_SIZE);
> - aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->ltpi),
> - "aspeed.ltpi",
> - sc->memmap[ASPEED_DEV_LTPI],
> - AST2700_SOC_LTPI_SIZE);
> aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem),
> "aspeed.io",
> sc->memmap[ASPEED_DEV_IOMEM],
> @@ -1143,6 +1152,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
> sc->macs_num = 3;
> sc->uarts_num = 13;
> sc->num_cpus = 4;
> + sc->ioexp_num = 0;
> sc->uarts_base = ASPEED_DEV_UART0;
> sc->irqmap = aspeed_soc_ast2700a1_irqmap;
> sc->memmap = aspeed_soc_ast2700_memmap;
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-12-24 10:39 ` Cédric Le Goater
@ 2025-12-29 19:37 ` Nabih Estefan
0 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:37 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee
On Wed, Dec 24, 2025 at 2:39 AM Cédric Le Goater <clg@kaod.org> wrote:
>
> On 12/24/25 02:41, Kane Chen via wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > Connect the AST1700 interrupt lines to the GIC in AST27X0, enabling
> > the propagation of AST1700-originated interrupts to the host SoC.
> >
> > This patch does not implement interrupt sources in AST1700 itself,
> > only the wiring into AST27X0.
> >
> > Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
I agree with the readability notes from Cedric, as for the bus naming,
I feel like that applied to patch 14 more than it does to this one.
>
> Thanks,
>
> C.
>
>
> > ---
> > include/hw/arm/aspeed_soc.h | 6 +++-
> > include/hw/intc/aspeed_intc.h | 2 ++
> > hw/arm/aspeed_ast27x0.c | 37 +++++++++++++++++++++
> > hw/intc/aspeed_intc.c | 60 +++++++++++++++++++++++++++++++++++
> > 4 files changed, 104 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> > index f19bab3457..b051d0eb3a 100644
> > --- a/include/hw/arm/aspeed_soc.h
> > +++ b/include/hw/arm/aspeed_soc.h
> > @@ -58,6 +58,7 @@
> > #define ASPEED_UARTS_NUM 13
> > #define ASPEED_JTAG_NUM 2
> > #define ASPEED_PCIE_NUM 3
> > +#define ASPEED_INTC_NUM 2
> > #define ASPEED_IOEXP_NUM 2
> >
> > struct AspeedSoCState {
> > @@ -146,7 +147,8 @@ struct Aspeed27x0SoCState {
> > AspeedSoCState parent;
> >
> > ARMCPU cpu[ASPEED_CPUS_NUM];
> > - AspeedINTCState intc[2];
> > + AspeedINTCState intc[ASPEED_INTC_NUM];
> > + AspeedINTCState intcioexp[ASPEED_IOEXP_NUM];
> > GICv3State gic;
> > MemoryRegion dram_empty;
> > };
> > @@ -288,6 +290,8 @@ enum {
> > ASPEED_DEV_LTPI_CTRL2,
> > ASPEED_DEV_LTPI_IO0,
> > ASPEED_DEV_LTPI_IO1,
> > + ASPEED_DEV_IOEXP0_INTCIO,
> > + ASPEED_DEV_IOEXP1_INTCIO,
> > };
> >
> > const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
> > diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
> > index 51288384a5..4565bbab84 100644
> > --- a/include/hw/intc/aspeed_intc.h
> > +++ b/include/hw/intc/aspeed_intc.h
> > @@ -15,6 +15,8 @@
> > #define TYPE_ASPEED_INTC "aspeed.intc"
> > #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
> > #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
> > +#define TYPE_ASPEED_2700_INTCIOEXP1 TYPE_ASPEED_INTC "ast2700-ioexp1"
> > +#define TYPE_ASPEED_2700_INTCIOEXP2 TYPE_ASPEED_INTC "ast2700-ioexp2"
> > #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
> > #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp"
> > #define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp"
> > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> > index de39a3e7eb..678d4eb6d9 100644
> > --- a/hw/arm/aspeed_ast27x0.c
> > +++ b/hw/arm/aspeed_ast27x0.c
> > @@ -91,7 +91,9 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> > [ASPEED_DEV_LTPI_CTRL2] = 0x14C35000,
> > [ASPEED_DEV_WDT] = 0x14C37000,
> > [ASPEED_DEV_LTPI_IO0] = 0x30000000,
> > + [ASPEED_DEV_IOEXP0_INTCIO] = 0x30C18000,
> > [ASPEED_DEV_LTPI_IO1] = 0x50000000,
> > + [ASPEED_DEV_IOEXP1_INTCIO] = 0x50C18000,
> > [ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
> > [ASPEED_DEV_PCIE_MMIO1] = 0x80000000,
> > [ASPEED_DEV_PCIE_MMIO2] = 0xA0000000,
> > @@ -511,6 +513,10 @@ static void aspeed_soc_ast2700_init(Object *obj)
> > object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC);
> > object_initialize_child(obj, "intcio", &a->intc[1],
> > TYPE_ASPEED_2700_INTCIO);
> > + object_initialize_child(obj, "intcioexp0", &a->intcioexp[0],
> > + TYPE_ASPEED_2700_INTCIOEXP1);
> > + object_initialize_child(obj, "intcioexp1", &a->intcioexp[1],
> > + TYPE_ASPEED_2700_INTCIOEXP2);
> >
> > snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
> > object_initialize_child(obj, "adc", &s->adc, typename);
> > @@ -755,6 +761,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> > aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0,
> > sc->memmap[ASPEED_DEV_INTCIO]);
> >
> > + /* INTCIOEXP0 */
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[0]), errp)) {
> > + return;
> > + }
> > +
> > + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[0]), 0,
> > + sc->memmap[ASPEED_DEV_IOEXP0_INTCIO]);
> > +
> > + /* INTCIOEXP1 */
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[1]), errp)) {
> > + return;
> > + }
> > +
> > + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[1]), 0,
> > + sc->memmap[ASPEED_DEV_IOEXP1_INTCIO]);
> > +
> > /* irq sources -> orgates -> INTC */
> > for (i = 0; i < ic->num_inpins; i++) {
> > qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
> > @@ -1079,6 +1101,21 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> > }
> > sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0,
> > sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
> > +
> > + icio = ASPEED_INTC_GET_CLASS(&a->intcioexp[i]);
> > + /* INTC_IOEXP internal: orgate[i] -> input[i] */
> > + for (int j = 0; j < icio->num_inpins; j++) {
> > + irq = qdev_get_gpio_in(DEVICE(&a->intcioexp[i]), j);
> > + qdev_connect_gpio_out(DEVICE(&a->intcioexp[i].orgates[j]), 0,
> > + irq);
> > + }
> > +
> > + /* INTC_IOEXP output[i] -> INTC0.orgate[0].input[i] */
> > + for (int j = 0; j < icio->num_outpins; j++) {
> > + irq = qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), j);
> > + sysbus_connect_irq(SYS_BUS_DEVICE(&a->intcioexp[i]), j,
> > + irq);
> > + }
> > }
> >
> > aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
> > diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
> > index 5cd786dee6..a04005ee7c 100644
> > --- a/hw/intc/aspeed_intc.c
> > +++ b/hw/intc/aspeed_intc.c
> > @@ -924,6 +924,64 @@ static const TypeInfo aspeed_2700_intc_info = {
> > .class_init = aspeed_2700_intc_class_init,
> > };
> >
> > +static AspeedINTCIRQ aspeed_2700_intcioexp2_irqs[ASPEED_INTC_MAX_INPINS] = {
> > + {0, 8, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> > + {1, 9, 1, R_GICINT193_EN, R_GICINT193_STATUS},
> > +};
> > +
> > +static void aspeed_2700_intcioexp2_class_init(ObjectClass *klass,
> > + const void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
> > +
> > + dc->desc = "ASPEED 2700 IOEXP2 INTC Controller";
> > + aic->num_lines = 32;
> > + aic->num_inpins = 2;
> > + aic->num_outpins = 10;
> > + aic->mem_size = 0x400;
> > + aic->nr_regs = 0x58 >> 2;
> > + aic->reg_offset = 0x100;
> > + aic->reg_ops = &aspeed_intcio_ops;
> > + aic->irq_table = aspeed_2700_intcioexp2_irqs;
> > + aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcioexp2_irqs);
> > +}
> > +
> > +static const TypeInfo aspeed_2700_intcioexp2_info = {
> > + .name = TYPE_ASPEED_2700_INTCIOEXP2,
> > + .parent = TYPE_ASPEED_INTC,
> > + .class_init = aspeed_2700_intcioexp2_class_init,
> > +};
> > +
> > +static AspeedINTCIRQ aspeed_2700_intcioexp1_irqs[ASPEED_INTC_MAX_INPINS] = {
> > + {0, 6, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> > + {1, 7, 1, R_GICINT193_EN, R_GICINT193_STATUS},
> > +};
> > +
> > +static void aspeed_2700_intcioexp1_class_init(ObjectClass *klass,
> > + const void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
> > +
> > + dc->desc = "ASPEED 2700 IOEXP1 INTC Controller";
> > + aic->num_lines = 32;
> > + aic->num_inpins = 2;
> > + aic->num_outpins = 10;
> > + aic->mem_size = 0x400;
> > + aic->nr_regs = 0x58 >> 2;
> > + aic->reg_offset = 0x100;
> > + aic->reg_ops = &aspeed_intcio_ops;
> > + aic->irq_table = aspeed_2700_intcioexp1_irqs;
> > + aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcioexp1_irqs);
> > +}
> > +
> > +static const TypeInfo aspeed_2700_intcioexp1_info = {
> > + .name = TYPE_ASPEED_2700_INTCIOEXP1,
> > + .parent = TYPE_ASPEED_INTC,
> > + .class_init = aspeed_2700_intcioexp1_class_init,
> > +};
> > +
> > static AspeedINTCIRQ aspeed_2700_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
> > {0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS},
> > {1, 1, 1, R_GICINT193_EN, R_GICINT193_STATUS},
> > @@ -1099,6 +1157,8 @@ static void aspeed_intc_register_types(void)
> > type_register_static(&aspeed_intc_info);
> > type_register_static(&aspeed_2700_intc_info);
> > type_register_static(&aspeed_2700_intcio_info);
> > + type_register_static(&aspeed_2700_intcioexp1_info);
> > + type_register_static(&aspeed_2700_intcioexp2_info);
> > type_register_static(&aspeed_2700ssp_intc_info);
> > type_register_static(&aspeed_2700ssp_intcio_info);
> > type_register_static(&aspeed_2700tsp_intc_info);
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 07/19] hw/arm/aspeed: Attach LTPI controller to AST1700 model
2025-12-24 10:41 ` Cédric Le Goater
@ 2025-12-29 19:38 ` Nabih Estefan
0 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:38 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee
On Wed, Dec 24, 2025 at 2:41 AM Cédric Le Goater <clg@kaod.org> wrote:
>
> On 12/24/25 02:41, Kane Chen via wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > Connect the LTPI controller to the AST1700 model by mapping its MMIO
> > region.
> >
> > Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
>
>
> > ---
> > include/hw/arm/aspeed_ast1700.h | 3 +++
> > hw/arm/aspeed_ast1700.c | 27 +++++++++++++++++++++++++++
> > 2 files changed, 30 insertions(+)
> >
> > diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
> > index 2a95ebfe89..b9ee4952d0 100644
> > --- a/include/hw/arm/aspeed_ast1700.h
> > +++ b/include/hw/arm/aspeed_ast1700.h
> > @@ -9,6 +9,7 @@
> > #define ASPEED_AST1700_H
> >
> > #include "hw/sysbus.h"
> > +#include "hw/misc/aspeed_ltpi.h"
> >
> > #define TYPE_ASPEED_AST1700 "aspeed.ast1700"
> >
> > @@ -18,6 +19,8 @@ struct AspeedAST1700SoCState {
> > SysBusDevice parent_obj;
> >
> > MemoryRegion iomem;
> > +
> > + AspeedLTPIState ltpi;
> > };
> >
> > #endif /* ASPEED_AST1700_H */
> > diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
> > index bb6ca2ce9e..eeb586102f 100644
> > --- a/hw/arm/aspeed_ast1700.c
> > +++ b/hw/arm/aspeed_ast1700.c
> > @@ -14,6 +14,14 @@
> >
> > #define AST2700_SOC_LTPI_SIZE 0x01000000
> >
> > +enum {
> > + ASPEED_AST1700_DEV_LTPI_CTRL,
> > +};
> > +
> > +static const hwaddr aspeed_ast1700_io_memmap[] = {
> > + [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> > +};
> > +
> > static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> > {
> > AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
> > @@ -23,8 +31,26 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> > memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700,
> > AST2700_SOC_LTPI_SIZE);
> > sysbus_init_mmio(sbd, &s->iomem);
> > +
> > + /* LTPI controller */
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
> > + return;
> > + }
> > + memory_region_add_subregion(&s->iomem,
> > + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_CTRL],
> > + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0));
> > }
> >
> > +static void aspeed_ast1700_instance_init(Object *obj)
> > +{
> > + AspeedAST1700SoCState *s = ASPEED_AST1700(obj);
> > +
> > + /* LTPI controller */
> > + object_initialize_child(obj, "ltpi-ctrl",
> > + &s->ltpi, TYPE_ASPEED_LTPI);
> > +
> > + return;
> > +}
> > static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data)
> > {
> > DeviceClass *dc = DEVICE_CLASS(klass);
> > @@ -37,6 +63,7 @@ static const TypeInfo aspeed_ast1700_info = {
> > .parent = TYPE_SYS_BUS_DEVICE,
> > .instance_size = sizeof(AspeedAST1700SoCState),
> > .class_init = aspeed_ast1700_class_init,
> > + .instance_init = aspeed_ast1700_instance_init,
> > };
> >
> > static void aspeed_ast1700_register_types(void)
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 08/19] hw/arm/aspeed: Attach UART device to AST1700 model
2025-12-24 1:41 ` [PATCH v4 08/19] hw/arm/aspeed: Attach UART device " Kane Chen via
@ 2025-12-29 19:38 ` Nabih Estefan
0 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:38 UTC (permalink / raw)
To: Kane Chen
Cc: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee, Cédric Le Goater
On Tue, Dec 23, 2025 at 5:42 PM Kane Chen <kane_chen@aspeedtech.com> wrote:
>
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the UART controller to the AST1700 model by mapping its MMIO
> region.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
> ---
> include/hw/arm/aspeed_ast1700.h | 2 ++
> hw/arm/aspeed_ast1700.c | 18 ++++++++++++++++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
> index b9ee4952d0..a0d6b3ae44 100644
> --- a/include/hw/arm/aspeed_ast1700.h
> +++ b/include/hw/arm/aspeed_ast1700.h
> @@ -10,6 +10,7 @@
>
> #include "hw/sysbus.h"
> #include "hw/misc/aspeed_ltpi.h"
> +#include "hw/char/serial-mm.h"
>
> #define TYPE_ASPEED_AST1700 "aspeed.ast1700"
>
> @@ -21,6 +22,7 @@ struct AspeedAST1700SoCState {
> MemoryRegion iomem;
>
> AspeedLTPIState ltpi;
> + SerialMM uart;
> };
>
> #endif /* ASPEED_AST1700_H */
> diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
> index eeb586102f..f444582795 100644
> --- a/hw/arm/aspeed_ast1700.c
> +++ b/hw/arm/aspeed_ast1700.c
> @@ -10,15 +10,18 @@
> #include "hw/boards.h"
> #include "hw/qdev-core.h"
> #include "qom/object.h"
> +#include "hw/qdev-properties.h"
> #include "hw/arm/aspeed_ast1700.h"
>
> #define AST2700_SOC_LTPI_SIZE 0x01000000
>
> enum {
> + ASPEED_AST1700_DEV_UART12,
> ASPEED_AST1700_DEV_LTPI_CTRL,
> };
>
> static const hwaddr aspeed_ast1700_io_memmap[] = {
> + [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> };
>
> @@ -32,6 +35,17 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> AST2700_SOC_LTPI_SIZE);
> sysbus_init_mmio(sbd, &s->iomem);
>
> + /* UART */
> + qdev_prop_set_uint8(DEVICE(&s->uart), "regshift", 2);
> + qdev_prop_set_uint32(DEVICE(&s->uart), "baudbase", 38400);
> + qdev_prop_set_uint8(DEVICE(&s->uart), "endianness", DEVICE_LITTLE_ENDIAN);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
> + return;
> + }
> + memory_region_add_subregion(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12],
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0));
> +
> /* LTPI controller */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
> return;
> @@ -45,6 +59,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
> {
> AspeedAST1700SoCState *s = ASPEED_AST1700(obj);
>
> + /* UART */
> + object_initialize_child(obj, "uart[*]", &s->uart,
> + TYPE_SERIAL_MM);
> +
> /* LTPI controller */
> object_initialize_child(obj, "ltpi-ctrl",
> &s->ltpi, TYPE_ASPEED_LTPI);
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 09/19] hw/arm/aspeed: Attach SRAM device to AST1700 model
2025-12-24 1:41 ` [PATCH v4 09/19] hw/arm/aspeed: Attach SRAM " Kane Chen via
@ 2025-12-29 19:38 ` Nabih Estefan
0 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:38 UTC (permalink / raw)
To: Kane Chen
Cc: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee, Cédric Le Goater
On Tue, Dec 23, 2025 at 5:42 PM Kane Chen <kane_chen@aspeedtech.com> wrote:
>
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Map the SRAM device to AST1700 model
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
> ---
> include/hw/arm/aspeed_ast1700.h | 2 ++
> hw/arm/aspeed_ast1700.c | 18 ++++++++++++++++++
> hw/arm/aspeed_ast27x0.c | 1 +
> 3 files changed, 21 insertions(+)
>
> diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
> index a0d6b3ae44..23588f7a81 100644
> --- a/include/hw/arm/aspeed_ast1700.h
> +++ b/include/hw/arm/aspeed_ast1700.h
> @@ -20,9 +20,11 @@ struct AspeedAST1700SoCState {
> SysBusDevice parent_obj;
>
> MemoryRegion iomem;
> + uint8_t board_idx;
>
> AspeedLTPIState ltpi;
> SerialMM uart;
> + MemoryRegion sram;
> };
>
> #endif /* ASPEED_AST1700_H */
> diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
> index f444582795..cb07d94054 100644
> --- a/hw/arm/aspeed_ast1700.c
> +++ b/hw/arm/aspeed_ast1700.c
> @@ -14,13 +14,16 @@
> #include "hw/arm/aspeed_ast1700.h"
>
> #define AST2700_SOC_LTPI_SIZE 0x01000000
> +#define AST1700_SOC_SRAM_SIZE 0x00040000
>
> enum {
> + ASPEED_AST1700_DEV_SRAM,
> ASPEED_AST1700_DEV_UART12,
> ASPEED_AST1700_DEV_LTPI_CTRL,
> };
>
> static const hwaddr aspeed_ast1700_io_memmap[] = {
> + [ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
> [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> };
> @@ -29,12 +32,21 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> {
> AspeedAST1700SoCState *s = ASPEED_AST1700(dev);
> SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> + char dev_name[32];
>
> /* Occupy memory space for all controllers in AST1700 */
> memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700,
> AST2700_SOC_LTPI_SIZE);
> sysbus_init_mmio(sbd, &s->iomem);
>
> + /* SRAM */
> + snprintf(dev_name, sizeof(dev_name), "aspeed.ioexp-sram.%d", s->board_idx);
> + memory_region_init_ram(&s->sram, OBJECT(s), dev_name,
> + AST1700_SOC_SRAM_SIZE, errp);
> + memory_region_add_subregion(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SRAM],
> + &s->sram);
> +
> /* UART */
> qdev_prop_set_uint8(DEVICE(&s->uart), "regshift", 2);
> qdev_prop_set_uint32(DEVICE(&s->uart), "baudbase", 38400);
> @@ -69,11 +81,17 @@ static void aspeed_ast1700_instance_init(Object *obj)
>
> return;
> }
> +
> +static const Property aspeed_ast1700_props[] = {
> + DEFINE_PROP_UINT8("board-idx", AspeedAST1700SoCState, board_idx, 0),
> +};
> +
> static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> dc->realize = aspeed_ast1700_realize;
> + device_class_set_props(dc, aspeed_ast1700_props);
> }
>
> static const TypeInfo aspeed_ast1700_info = {
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 678d4eb6d9..f2418e0e45 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -1096,6 +1096,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
>
> /* IO Expander */
> for (i = 0; i < sc->ioexp_num; i++) {
> + qdev_prop_set_uint8(DEVICE(&s->ioexp[i]), "board-idx", i);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) {
> return;
> }
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 10/19] hw/arm/aspeed: Attach SPI device to AST1700 model
2025-12-24 1:41 ` [PATCH v4 10/19] hw/arm/aspeed: Attach SPI " Kane Chen via
@ 2025-12-29 19:38 ` Nabih Estefan
0 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:38 UTC (permalink / raw)
To: Kane Chen
Cc: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee, Cédric Le Goater
On Tue, Dec 23, 2025 at 5:42 PM Kane Chen <kane_chen@aspeedtech.com> wrote:
>
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the SPI device to AST1700 model.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
> ---
> include/hw/arm/aspeed_ast1700.h | 2 ++
> hw/arm/aspeed_ast1700.c | 22 ++++++++++++++++++++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
> index 23588f7a81..5b120dd11a 100644
> --- a/include/hw/arm/aspeed_ast1700.h
> +++ b/include/hw/arm/aspeed_ast1700.h
> @@ -10,6 +10,7 @@
>
> #include "hw/sysbus.h"
> #include "hw/misc/aspeed_ltpi.h"
> +#include "hw/ssi/aspeed_smc.h"
> #include "hw/char/serial-mm.h"
>
> #define TYPE_ASPEED_AST1700 "aspeed.ast1700"
> @@ -25,6 +26,7 @@ struct AspeedAST1700SoCState {
> AspeedLTPIState ltpi;
> SerialMM uart;
> MemoryRegion sram;
> + AspeedSMCState spi;
> };
>
> #endif /* ASPEED_AST1700_H */
> diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
> index cb07d94054..fc09bb1aed 100644
> --- a/hw/arm/aspeed_ast1700.c
> +++ b/hw/arm/aspeed_ast1700.c
> @@ -17,15 +17,19 @@
> #define AST1700_SOC_SRAM_SIZE 0x00040000
>
> enum {
> + ASPEED_AST1700_DEV_SPI0,
> ASPEED_AST1700_DEV_SRAM,
> ASPEED_AST1700_DEV_UART12,
> ASPEED_AST1700_DEV_LTPI_CTRL,
> + ASPEED_AST1700_DEV_SPI0_MEM,
> };
>
> static const hwaddr aspeed_ast1700_io_memmap[] = {
> + [ASPEED_AST1700_DEV_SPI0] = 0x00030000,
> [ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
> [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> + [ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
> };
>
> static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> @@ -58,6 +62,20 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12],
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0));
>
> + /* SPI */
> + object_property_set_link(OBJECT(&s->spi), "dram",
> + OBJECT(&s->iomem), errp);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi), errp)) {
> + return;
> + }
> + memory_region_add_subregion(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0],
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 0));
> +
> + memory_region_add_subregion(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0_MEM],
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 1));
> +
> /* LTPI controller */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
> return;
> @@ -75,6 +93,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
> object_initialize_child(obj, "uart[*]", &s->uart,
> TYPE_SERIAL_MM);
>
> + /* SPI */
> + object_initialize_child(obj, "ioexp-spi[*]", &s->spi,
> + "aspeed.spi0-ast2700");
> +
> /* LTPI controller */
> object_initialize_child(obj, "ltpi-ctrl",
> &s->ltpi, TYPE_ASPEED_LTPI);
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 11/19] hw/arm/aspeed: Attach ADC device to AST1700 model
2025-12-24 1:41 ` [PATCH v4 11/19] hw/arm/aspeed: Attach ADC " Kane Chen via
@ 2025-12-29 19:38 ` Nabih Estefan
0 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:38 UTC (permalink / raw)
To: Kane Chen
Cc: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee, Cédric Le Goater
On Tue, Dec 23, 2025 at 5:42 PM Kane Chen <kane_chen@aspeedtech.com> wrote:
>
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the ADC device to AST1700 model.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
> ---
> include/hw/arm/aspeed_ast1700.h | 2 ++
> hw/arm/aspeed_ast1700.c | 14 ++++++++++++++
> hw/arm/aspeed_ast27x0.c | 5 +++++
> 3 files changed, 21 insertions(+)
>
> diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
> index 5b120dd11a..0c1216c4ba 100644
> --- a/include/hw/arm/aspeed_ast1700.h
> +++ b/include/hw/arm/aspeed_ast1700.h
> @@ -9,6 +9,7 @@
> #define ASPEED_AST1700_H
>
> #include "hw/sysbus.h"
> +#include "hw/adc/aspeed_adc.h"
> #include "hw/misc/aspeed_ltpi.h"
> #include "hw/ssi/aspeed_smc.h"
> #include "hw/char/serial-mm.h"
> @@ -27,6 +28,7 @@ struct AspeedAST1700SoCState {
> SerialMM uart;
> MemoryRegion sram;
> AspeedSMCState spi;
> + AspeedADCState adc;
> };
>
> #endif /* ASPEED_AST1700_H */
> diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
> index fc09bb1aed..e4d206045f 100644
> --- a/hw/arm/aspeed_ast1700.c
> +++ b/hw/arm/aspeed_ast1700.c
> @@ -19,6 +19,7 @@
> enum {
> ASPEED_AST1700_DEV_SPI0,
> ASPEED_AST1700_DEV_SRAM,
> + ASPEED_AST1700_DEV_ADC,
> ASPEED_AST1700_DEV_UART12,
> ASPEED_AST1700_DEV_LTPI_CTRL,
> ASPEED_AST1700_DEV_SPI0_MEM,
> @@ -27,6 +28,7 @@ enum {
> static const hwaddr aspeed_ast1700_io_memmap[] = {
> [ASPEED_AST1700_DEV_SPI0] = 0x00030000,
> [ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
> + [ASPEED_AST1700_DEV_ADC] = 0x00C00000,
> [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> [ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
> @@ -76,6 +78,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0_MEM],
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 1));
>
> + /* ADC */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
> + return;
> + }
> + memory_region_add_subregion(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_ADC],
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->adc), 0));
> +
> /* LTPI controller */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
> return;
> @@ -97,6 +107,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
> object_initialize_child(obj, "ioexp-spi[*]", &s->spi,
> "aspeed.spi0-ast2700");
>
> + /* ADC */
> + object_initialize_child(obj, "ioexp-adc[*]", &s->adc,
> + "aspeed.adc-ast2700");
> +
> /* LTPI controller */
> object_initialize_child(obj, "ltpi-ctrl",
> &s->ltpi, TYPE_ASPEED_LTPI);
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index f2418e0e45..84ff8b5557 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -1117,6 +1117,11 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&a->intcioexp[i]), j,
> irq);
> }
> +
> + /* ADC */
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].adc), 0,
> + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ADC));
> +
> }
>
> aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 12/19] hw/arm/aspeed: Attach SCU device to AST1700 model
2025-12-24 1:41 ` [PATCH v4 12/19] hw/arm/aspeed: Attach SCU " Kane Chen via
@ 2025-12-29 19:38 ` Nabih Estefan
0 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:38 UTC (permalink / raw)
To: Kane Chen
Cc: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee, Cédric Le Goater
On Tue, Dec 23, 2025 at 5:42 PM Kane Chen <kane_chen@aspeedtech.com> wrote:
>
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the SCU device to AST1700 model.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
> ---
> include/hw/arm/aspeed_ast1700.h | 3 +++
> hw/arm/aspeed_ast1700.c | 17 +++++++++++++++++
> hw/arm/aspeed_ast27x0.c | 2 ++
> 3 files changed, 22 insertions(+)
>
> diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
> index 0c1216c4ba..12c57145c6 100644
> --- a/include/hw/arm/aspeed_ast1700.h
> +++ b/include/hw/arm/aspeed_ast1700.h
> @@ -9,6 +9,7 @@
> #define ASPEED_AST1700_H
>
> #include "hw/sysbus.h"
> +#include "hw/misc/aspeed_scu.h"
> #include "hw/adc/aspeed_adc.h"
> #include "hw/misc/aspeed_ltpi.h"
> #include "hw/ssi/aspeed_smc.h"
> @@ -23,12 +24,14 @@ struct AspeedAST1700SoCState {
>
> MemoryRegion iomem;
> uint8_t board_idx;
> + uint32_t silicon_rev;
>
> AspeedLTPIState ltpi;
> SerialMM uart;
> MemoryRegion sram;
> AspeedSMCState spi;
> AspeedADCState adc;
> + AspeedSCUState scu;
> };
>
> #endif /* ASPEED_AST1700_H */
> diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
> index e4d206045f..6494a5c4eb 100644
> --- a/hw/arm/aspeed_ast1700.c
> +++ b/hw/arm/aspeed_ast1700.c
> @@ -20,6 +20,7 @@ enum {
> ASPEED_AST1700_DEV_SPI0,
> ASPEED_AST1700_DEV_SRAM,
> ASPEED_AST1700_DEV_ADC,
> + ASPEED_AST1700_DEV_SCU,
> ASPEED_AST1700_DEV_UART12,
> ASPEED_AST1700_DEV_LTPI_CTRL,
> ASPEED_AST1700_DEV_SPI0_MEM,
> @@ -29,6 +30,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
> [ASPEED_AST1700_DEV_SPI0] = 0x00030000,
> [ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
> [ASPEED_AST1700_DEV_ADC] = 0x00C00000,
> + [ASPEED_AST1700_DEV_SCU] = 0x00C02000,
> [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> [ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
> @@ -86,6 +88,16 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_ADC],
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->adc), 0));
>
> + /* SCU */
> + qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
> + s->silicon_rev);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
> + return;
> + }
> + memory_region_add_subregion(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SCU],
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->scu), 0));
> +
> /* LTPI controller */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
> return;
> @@ -111,6 +123,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
> object_initialize_child(obj, "ioexp-adc[*]", &s->adc,
> "aspeed.adc-ast2700");
>
> + /* SCU */
> + object_initialize_child(obj, "ioexp-scu[*]", &s->scu,
> + TYPE_ASPEED_2700_SCU);
> +
> /* LTPI controller */
> object_initialize_child(obj, "ltpi-ctrl",
> &s->ltpi, TYPE_ASPEED_LTPI);
> @@ -120,6 +136,7 @@ static void aspeed_ast1700_instance_init(Object *obj)
>
> static const Property aspeed_ast1700_props[] = {
> DEFINE_PROP_UINT8("board-idx", AspeedAST1700SoCState, board_idx, 0),
> + DEFINE_PROP_UINT32("silicon-rev", AspeedAST1700SoCState, silicon_rev, 0),
> };
>
> static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data)
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 84ff8b5557..6b9ad328dc 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -573,6 +573,8 @@ static void aspeed_soc_ast2700_init(Object *obj)
> /* AST1700 IOEXP */
> object_initialize_child(obj, "ioexp[*]", &s->ioexp[i],
> TYPE_ASPEED_AST1700);
> + qdev_prop_set_uint32(DEVICE(&s->ioexp[i]), "silicon-rev",
> + sc->silicon_rev);
> }
>
> object_initialize_child(obj, "dpmcu", &s->dpmcu,
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 13/19] hw/arm/aspeed: Attach GPIO device to AST1700 model
2025-12-24 1:41 ` [PATCH v4 13/19] hw/arm/aspeed: Attach GPIO " Kane Chen via
@ 2025-12-29 19:38 ` Nabih Estefan
0 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:38 UTC (permalink / raw)
To: Kane Chen
Cc: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee, Cédric Le Goater
On Tue, Dec 23, 2025 at 5:42 PM Kane Chen <kane_chen@aspeedtech.com> wrote:
>
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the GPIO controller to the AST1700 model by mapping its MMIO
> region and wiring its interrupt line.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
> ---
> include/hw/arm/aspeed_ast1700.h | 2 ++
> hw/arm/aspeed_ast1700.c | 14 ++++++++++++++
> hw/arm/aspeed_ast27x0.c | 4 ++++
> 3 files changed, 20 insertions(+)
>
> diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
> index 12c57145c6..7ea6ff4c1a 100644
> --- a/include/hw/arm/aspeed_ast1700.h
> +++ b/include/hw/arm/aspeed_ast1700.h
> @@ -11,6 +11,7 @@
> #include "hw/sysbus.h"
> #include "hw/misc/aspeed_scu.h"
> #include "hw/adc/aspeed_adc.h"
> +#include "hw/gpio/aspeed_gpio.h"
> #include "hw/misc/aspeed_ltpi.h"
> #include "hw/ssi/aspeed_smc.h"
> #include "hw/char/serial-mm.h"
> @@ -32,6 +33,7 @@ struct AspeedAST1700SoCState {
> AspeedSMCState spi;
> AspeedADCState adc;
> AspeedSCUState scu;
> + AspeedGPIOState gpio;
> };
>
> #endif /* ASPEED_AST1700_H */
> diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
> index 6494a5c4eb..9a6019908e 100644
> --- a/hw/arm/aspeed_ast1700.c
> +++ b/hw/arm/aspeed_ast1700.c
> @@ -21,6 +21,7 @@ enum {
> ASPEED_AST1700_DEV_SRAM,
> ASPEED_AST1700_DEV_ADC,
> ASPEED_AST1700_DEV_SCU,
> + ASPEED_AST1700_DEV_GPIO,
> ASPEED_AST1700_DEV_UART12,
> ASPEED_AST1700_DEV_LTPI_CTRL,
> ASPEED_AST1700_DEV_SPI0_MEM,
> @@ -31,6 +32,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
> [ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
> [ASPEED_AST1700_DEV_ADC] = 0x00C00000,
> [ASPEED_AST1700_DEV_SCU] = 0x00C02000,
> + [ASPEED_AST1700_DEV_GPIO] = 0x00C0B000,
> [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> [ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
> @@ -98,6 +100,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SCU],
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->scu), 0));
>
> + /* GPIO */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
> + return;
> + }
> + memory_region_add_subregion(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_GPIO],
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0));
> +
> /* LTPI controller */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
> return;
> @@ -127,6 +137,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
> object_initialize_child(obj, "ioexp-scu[*]", &s->scu,
> TYPE_ASPEED_2700_SCU);
>
> + /* GPIO */
> + object_initialize_child(obj, "ioexp-gpio[*]", &s->gpio,
> + "aspeed.gpio-ast2700");
> +
> /* LTPI controller */
> object_initialize_child(obj, "ltpi-ctrl",
> &s->ltpi, TYPE_ASPEED_LTPI);
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 6b9ad328dc..d998326536 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -1124,6 +1124,10 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].adc), 0,
> aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ADC));
>
> + /* GPIO */
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].gpio), 0,
> + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO));
> +
> }
>
> aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 15/19] hw/arm/aspeed: Attach WDT device to AST1700 model
2025-12-24 1:41 ` [PATCH v4 15/19] hw/arm/aspeed: Attach WDT " Kane Chen via
@ 2025-12-29 19:38 ` Nabih Estefan
0 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:38 UTC (permalink / raw)
To: Kane Chen
Cc: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee, Cédric Le Goater
On Tue, Dec 23, 2025 at 5:42 PM Kane Chen <kane_chen@aspeedtech.com> wrote:
>
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the WDT device to AST1700 model.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
> ---
> include/hw/arm/aspeed_ast1700.h | 4 ++++
> hw/arm/aspeed_ast1700.c | 24 ++++++++++++++++++++++++
> 2 files changed, 28 insertions(+)
>
> diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
> index d4b7abee7d..f43c0c5475 100644
> --- a/include/hw/arm/aspeed_ast1700.h
> +++ b/include/hw/arm/aspeed_ast1700.h
> @@ -15,8 +15,11 @@
> #include "hw/i2c/aspeed_i2c.h"
> #include "hw/misc/aspeed_ltpi.h"
> #include "hw/ssi/aspeed_smc.h"
> +#include "hw/watchdog/wdt_aspeed.h"
> #include "hw/char/serial-mm.h"
>
> +#define AST1700_WDT_NUM 9
> +
> #define TYPE_ASPEED_AST1700 "aspeed.ast1700"
>
> OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700)
> @@ -36,6 +39,7 @@ struct AspeedAST1700SoCState {
> AspeedSCUState scu;
> AspeedGPIOState gpio;
> AspeedI2CState i2c;
> + AspeedWDTState wdt[AST1700_WDT_NUM];
> };
>
> #endif /* ASPEED_AST1700_H */
> diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
> index fad3b86e8d..9fb84dd159 100644
> --- a/hw/arm/aspeed_ast1700.c
> +++ b/hw/arm/aspeed_ast1700.c
> @@ -25,6 +25,7 @@ enum {
> ASPEED_AST1700_DEV_I2C,
> ASPEED_AST1700_DEV_UART12,
> ASPEED_AST1700_DEV_LTPI_CTRL,
> + ASPEED_AST1700_DEV_WDT,
> ASPEED_AST1700_DEV_SPI0_MEM,
> };
>
> @@ -37,6 +38,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
> [ASPEED_AST1700_DEV_I2C] = 0x00C0F000,
> [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> + [ASPEED_AST1700_DEV_WDT] = 0x00C37000,
> [ASPEED_AST1700_DEV_SPI0_MEM] = 0x04000000,
> };
>
> @@ -129,6 +131,22 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> memory_region_add_subregion(&s->iomem,
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_CTRL],
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0));
> + /* WDT */
> + for (int i = 0; i < AST1700_WDT_NUM; i++) {
> + AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
> + hwaddr wdt_offset = aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_WDT] +
> + i * awc->iosize;
> +
> + object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
> + errp);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
> + return;
> + }
> + memory_region_add_subregion(&s->iomem,
> + wdt_offset,
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->wdt[i]), 0));
> + }
> +
> }
>
> static void aspeed_ast1700_instance_init(Object *obj)
> @@ -163,6 +181,12 @@ static void aspeed_ast1700_instance_init(Object *obj)
> object_initialize_child(obj, "ltpi-ctrl",
> &s->ltpi, TYPE_ASPEED_LTPI);
>
> + /* WDT */
> + for (int i = 0; i < AST1700_WDT_NUM; i++) {
> + object_initialize_child(obj, "ioexp-wdt[*]",
> + &s->wdt[i], "aspeed.wdt-ast2700");
> + }
> +
> return;
> }
>
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 16/19] hw/arm/aspeed: Attach PWM device to AST1700 model
2025-12-24 1:41 ` [PATCH v4 16/19] hw/arm/aspeed: Attach PWM " Kane Chen via
@ 2025-12-29 19:38 ` Nabih Estefan
0 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:38 UTC (permalink / raw)
To: Kane Chen
Cc: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee, Cédric Le Goater
On Tue, Dec 23, 2025 at 5:42 PM Kane Chen <kane_chen@aspeedtech.com> wrote:
>
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the PWM device to AST1700 model.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
> ---
> include/hw/arm/aspeed_ast1700.h | 2 ++
> hw/arm/aspeed_ast1700.c | 13 +++++++++++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
> index f43c0c5475..7292719dc2 100644
> --- a/include/hw/arm/aspeed_ast1700.h
> +++ b/include/hw/arm/aspeed_ast1700.h
> @@ -14,6 +14,7 @@
> #include "hw/gpio/aspeed_gpio.h"
> #include "hw/i2c/aspeed_i2c.h"
> #include "hw/misc/aspeed_ltpi.h"
> +#include "hw/misc/aspeed_pwm.h"
> #include "hw/ssi/aspeed_smc.h"
> #include "hw/watchdog/wdt_aspeed.h"
> #include "hw/char/serial-mm.h"
> @@ -39,6 +40,7 @@ struct AspeedAST1700SoCState {
> AspeedSCUState scu;
> AspeedGPIOState gpio;
> AspeedI2CState i2c;
> + AspeedPWMState pwm;
> AspeedWDTState wdt[AST1700_WDT_NUM];
> };
>
> diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
> index 9fb84dd159..5a2552aa25 100644
> --- a/hw/arm/aspeed_ast1700.c
> +++ b/hw/arm/aspeed_ast1700.c
> @@ -18,6 +18,7 @@
>
> enum {
> ASPEED_AST1700_DEV_SPI0,
> + ASPEED_AST1700_DEV_PWM,
> ASPEED_AST1700_DEV_SRAM,
> ASPEED_AST1700_DEV_ADC,
> ASPEED_AST1700_DEV_SCU,
> @@ -31,6 +32,7 @@ enum {
>
> static const hwaddr aspeed_ast1700_io_memmap[] = {
> [ASPEED_AST1700_DEV_SPI0] = 0x00030000,
> + [ASPEED_AST1700_DEV_PWM] = 0x000C0000,
> [ASPEED_AST1700_DEV_SRAM] = 0x00BC0000,
> [ASPEED_AST1700_DEV_ADC] = 0x00C00000,
> [ASPEED_AST1700_DEV_SCU] = 0x00C02000,
> @@ -124,6 +126,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I2C],
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c), 0));
>
> + /* PWM */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm), errp)) {
> + return;
> + }
> + memory_region_add_subregion(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_PWM],
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pwm), 0));
> +
> /* LTPI controller */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) {
> return;
> @@ -177,6 +187,9 @@ static void aspeed_ast1700_instance_init(Object *obj)
> object_initialize_child(obj, "ioexp-i2c[*]", &s->i2c,
> "aspeed.i2c-ast2700");
>
> + /* PWM */
> + object_initialize_child(obj, "pwm", &s->pwm, TYPE_ASPEED_PWM);
> +
> /* LTPI controller */
> object_initialize_child(obj, "ltpi-ctrl",
> &s->ltpi, TYPE_ASPEED_LTPI);
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 17/19] hw/arm/aspeed: Attach SGPIOM device to AST1700 model
2025-12-24 1:41 ` [PATCH v4 17/19] hw/arm/aspeed: Attach SGPIOM " Kane Chen via
@ 2025-12-29 19:38 ` Nabih Estefan
0 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:38 UTC (permalink / raw)
To: Kane Chen
Cc: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee, Cédric Le Goater
On Tue, Dec 23, 2025 at 5:42 PM Kane Chen <kane_chen@aspeedtech.com> wrote:
>
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Connect the SGPIOM device to AST1700 model.
>
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
> ---
> include/hw/arm/aspeed_ast1700.h | 3 +++
> hw/arm/aspeed_ast1700.c | 21 +++++++++++++++++++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
> index 7292719dc2..490f2a3b05 100644
> --- a/include/hw/arm/aspeed_ast1700.h
> +++ b/include/hw/arm/aspeed_ast1700.h
> @@ -12,6 +12,7 @@
> #include "hw/misc/aspeed_scu.h"
> #include "hw/adc/aspeed_adc.h"
> #include "hw/gpio/aspeed_gpio.h"
> +#include "hw/gpio/aspeed_sgpio.h"
> #include "hw/i2c/aspeed_i2c.h"
> #include "hw/misc/aspeed_ltpi.h"
> #include "hw/misc/aspeed_pwm.h"
> @@ -19,6 +20,7 @@
> #include "hw/watchdog/wdt_aspeed.h"
> #include "hw/char/serial-mm.h"
>
> +#define AST1700_SGPIO_NUM 2
> #define AST1700_WDT_NUM 9
>
> #define TYPE_ASPEED_AST1700 "aspeed.ast1700"
> @@ -39,6 +41,7 @@ struct AspeedAST1700SoCState {
> AspeedADCState adc;
> AspeedSCUState scu;
> AspeedGPIOState gpio;
> + AspeedSGPIOState sgpiom[AST1700_SGPIO_NUM];
> AspeedI2CState i2c;
> AspeedPWMState pwm;
> AspeedWDTState wdt[AST1700_WDT_NUM];
> diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
> index 5a2552aa25..ca0ce4e2c2 100644
> --- a/hw/arm/aspeed_ast1700.c
> +++ b/hw/arm/aspeed_ast1700.c
> @@ -23,6 +23,8 @@ enum {
> ASPEED_AST1700_DEV_ADC,
> ASPEED_AST1700_DEV_SCU,
> ASPEED_AST1700_DEV_GPIO,
> + ASPEED_AST1700_DEV_SGPIOM0,
> + ASPEED_AST1700_DEV_SGPIOM1,
> ASPEED_AST1700_DEV_I2C,
> ASPEED_AST1700_DEV_UART12,
> ASPEED_AST1700_DEV_LTPI_CTRL,
> @@ -37,6 +39,8 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
> [ASPEED_AST1700_DEV_ADC] = 0x00C00000,
> [ASPEED_AST1700_DEV_SCU] = 0x00C02000,
> [ASPEED_AST1700_DEV_GPIO] = 0x00C0B000,
> + [ASPEED_AST1700_DEV_SGPIOM0] = 0x00C0C000,
> + [ASPEED_AST1700_DEV_SGPIOM1] = 0x00C0D000,
> [ASPEED_AST1700_DEV_I2C] = 0x00C0F000,
> [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> @@ -141,6 +145,17 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> memory_region_add_subregion(&s->iomem,
> aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_CTRL],
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0));
> +
> + /* SGPIOM */
> + for (int i = 0; i < AST1700_SGPIO_NUM; i++) {
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->sgpiom[i]), errp)) {
> + return;
> + }
> + memory_region_add_subregion(&s->iomem,
> + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SGPIOM0 + i],
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sgpiom[i]), 0));
> + }
> +
> /* WDT */
> for (int i = 0; i < AST1700_WDT_NUM; i++) {
> AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
> @@ -194,6 +209,12 @@ static void aspeed_ast1700_instance_init(Object *obj)
> object_initialize_child(obj, "ltpi-ctrl",
> &s->ltpi, TYPE_ASPEED_LTPI);
>
> + /* SGPIOM */
> + for (int i = 0; i < AST1700_SGPIO_NUM; i++) {
> + object_initialize_child(obj, "ioexp-sgpiom[*]", &s->sgpiom[i],
> + "aspeed.sgpio-ast2700");
> + }
> +
> /* WDT */
> for (int i = 0; i < AST1700_WDT_NUM; i++) {
> object_initialize_child(obj, "ioexp-wdt[*]",
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 18/19] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device
2025-12-24 10:43 ` Cédric Le Goater
@ 2025-12-29 19:38 ` Nabih Estefan
0 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:38 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee
On Wed, Dec 24, 2025 at 2:43 AM Cédric Le Goater <clg@kaod.org> wrote:
>
> On 12/24/25 02:41, Kane Chen via wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > AST1700 exposes more I3C buses than the current dummy I3C model
> > provides. When Linux probes the I3C devices on AST1700 this mismatch
> > can trigger a kernel panic. Model the I3C block as an unimplemented
> > device to make the missing functionality explicit and avoid unexpected
> > side effects.
> >
> > This wires up the I3C interrupt lines for the IO expanders and adds the
> > corresponding device entries for the AST1700 model.
> >
> > No functional I3C emulation is provided yet; this only prevents crashes and
> > documents the missing piece.
> >
> > Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
>
> Thanks,
>
> C.
>
> > ---
> > include/hw/arm/aspeed_ast1700.h | 3 +++
> > include/hw/arm/aspeed_soc.h | 2 ++
> > hw/arm/aspeed_ast1700.c | 15 +++++++++++++++
> > hw/arm/aspeed_ast27x0.c | 18 ++++++++++++++++--
> > 4 files changed, 36 insertions(+), 2 deletions(-)
> >
> > diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast1700.h
> > index 490f2a3b05..874b4d63fe 100644
> > --- a/include/hw/arm/aspeed_ast1700.h
> > +++ b/include/hw/arm/aspeed_ast1700.h
> > @@ -19,6 +19,7 @@
> > #include "hw/ssi/aspeed_smc.h"
> > #include "hw/watchdog/wdt_aspeed.h"
> > #include "hw/char/serial-mm.h"
> > +#include "hw/misc/unimp.h"
> >
> > #define AST1700_SGPIO_NUM 2
> > #define AST1700_WDT_NUM 9
> > @@ -45,6 +46,8 @@ struct AspeedAST1700SoCState {
> > AspeedI2CState i2c;
> > AspeedPWMState pwm;
> > AspeedWDTState wdt[AST1700_WDT_NUM];
> > +
> > + UnimplementedDeviceState i3c;
> > };
> >
> > #endif /* ASPEED_AST1700_H */
> > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> > index 4ea2521041..b185b04186 100644
> > --- a/include/hw/arm/aspeed_soc.h
> > +++ b/include/hw/arm/aspeed_soc.h
> > @@ -294,6 +294,8 @@ enum {
> > ASPEED_DEV_IOEXP1_I2C,
> > ASPEED_DEV_IOEXP0_INTCIO,
> > ASPEED_DEV_IOEXP1_INTCIO,
> > + ASPEED_DEV_IOEXP0_I3C,
> > + ASPEED_DEV_IOEXP1_I3C,
> > };
> >
> > const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
> > diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c
> > index ca0ce4e2c2..5f3c56e6cc 100644
> > --- a/hw/arm/aspeed_ast1700.c
> > +++ b/hw/arm/aspeed_ast1700.c
> > @@ -15,6 +15,7 @@
> >
> > #define AST2700_SOC_LTPI_SIZE 0x01000000
> > #define AST1700_SOC_SRAM_SIZE 0x00040000
> > +#define AST1700_SOC_I3C_SIZE 0x00010000
> >
> > enum {
> > ASPEED_AST1700_DEV_SPI0,
> > @@ -26,6 +27,7 @@ enum {
> > ASPEED_AST1700_DEV_SGPIOM0,
> > ASPEED_AST1700_DEV_SGPIOM1,
> > ASPEED_AST1700_DEV_I2C,
> > + ASPEED_AST1700_DEV_I3C,
> > ASPEED_AST1700_DEV_UART12,
> > ASPEED_AST1700_DEV_LTPI_CTRL,
> > ASPEED_AST1700_DEV_WDT,
> > @@ -42,6 +44,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] = {
> > [ASPEED_AST1700_DEV_SGPIOM0] = 0x00C0C000,
> > [ASPEED_AST1700_DEV_SGPIOM1] = 0x00C0D000,
> > [ASPEED_AST1700_DEV_I2C] = 0x00C0F000,
> > + [ASPEED_AST1700_DEV_I3C] = 0x00C20000,
> > [ASPEED_AST1700_DEV_UART12] = 0x00C33B00,
> > [ASPEED_AST1700_DEV_LTPI_CTRL] = 0x00C34000,
> > [ASPEED_AST1700_DEV_WDT] = 0x00C37000,
> > @@ -172,6 +175,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, Error **errp)
> > sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->wdt[i]), 0));
> > }
> >
> > + /* I3C */
> > + qdev_prop_set_string(DEVICE(&s->i3c), "name", "ioexp-i3c");
> > + qdev_prop_set_uint64(DEVICE(&s->i3c), "size", AST1700_SOC_I3C_SIZE);
> > + sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp);
> > + memory_region_add_subregion_overlap(&s->iomem,
> > + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I3C],
> > + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i3c), 0),
> > + -1000);
> > }
> >
> > static void aspeed_ast1700_instance_init(Object *obj)
> > @@ -221,6 +232,10 @@ static void aspeed_ast1700_instance_init(Object *obj)
> > &s->wdt[i], "aspeed.wdt-ast2700");
> > }
> >
> > + /* I3C */
> > + object_initialize_child(obj, "ioexp-i3c[*]", &s->i3c,
> > + TYPE_UNIMPLEMENTED_DEVICE);
> > +
> > return;
> > }
> >
> > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> > index ca3adf9a50..0807481162 100644
> > --- a/hw/arm/aspeed_ast27x0.c
> > +++ b/hw/arm/aspeed_ast27x0.c
> > @@ -206,7 +206,9 @@ static const int aspeed_soc_ast2700a1_irqmap[] = {
> > [ASPEED_DEV_PECI] = 197,
> > [ASPEED_DEV_SDHCI] = 197,
> > [ASPEED_DEV_IOEXP0_I2C] = 198,
> > + [ASPEED_DEV_IOEXP0_I3C] = 199,
> > [ASPEED_DEV_IOEXP1_I2C] = 200,
> > + [ASPEED_DEV_IOEXP1_I3C] = 201,
> > };
> >
> > /* GICINT 128 */
> > @@ -275,12 +277,24 @@ static const int ast2700_gic198_intcmap[] = {
> > [ASPEED_DEV_IOEXP0_I2C] = 0, /* 0 - 15 */
> > };
> >
> > +/* Primary AST1700 Interrupts */
> > +/* A1: GINTC 199 */
> > +static const int ast2700_gic199_intcmap[] = {
> > + [ASPEED_DEV_IOEXP0_I3C] = 0, /* 0 - 15 */
> > +};
> > +
> > /* Secondary AST1700 Interrupts */
> > /* A1: GINTC 200 */
> > static const int ast2700_gic200_intcmap[] = {
> > [ASPEED_DEV_IOEXP1_I2C] = 0, /* 0 - 15 */
> > };
> >
> > +/* Secondary AST1700 Interrupts */
> > +/* A1: GINTC 201 */
> > +static const int ast2700_gic201_intcmap[] = {
> > + [ASPEED_DEV_IOEXP1_I3C] = 0, /* 0 - 15 */
> > +};
> > +
> > /* GICINT 128 ~ 136 */
> > /* GICINT 192 ~ 201 */
> > struct gic_intc_irq_info {
> > @@ -298,9 +312,9 @@ static const struct gic_intc_irq_info ast2700_gic_intcmap[] = {
> > {196, 1, 4, ast2700_gic132_gic196_intcmap},
> > {197, 1, 5, ast2700_gic133_gic197_intcmap},
> > {198, 2, 0, ast2700_gic198_intcmap},
> > - {199, 1, 7, NULL},
> > + {199, 2, 1, ast2700_gic199_intcmap},
> > {200, 3, 0, ast2700_gic200_intcmap},
> > - {201, 1, 9, NULL},
> > + {201, 3, 1, ast2700_gic201_intcmap},
> > {128, 0, 1, ast2700_gic128_gic192_intcmap},
> > {129, 0, 2, NULL},
> > {130, 0, 3, ast2700_gic130_gic194_intcmap},
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 19/19] hw/arm/aspeed: Enable AST1700 IO expander support
2025-12-24 10:43 ` Cédric Le Goater
@ 2025-12-29 19:38 ` Nabih Estefan
0 siblings, 0 replies; 74+ messages in thread
From: Nabih Estefan @ 2025-12-29 19:38 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee
On Wed, Dec 24, 2025 at 2:43 AM Cédric Le Goater <clg@kaod.org> wrote:
>
> On 12/24/25 02:41, Kane Chen via wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > Set ioexp_num to 2 to enable AST1700 IO expander support.
> >
> > Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> > ---
> > hw/arm/aspeed_ast27x0.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> > index 0807481162..2eb857b8e0 100644
> > --- a/hw/arm/aspeed_ast27x0.c
> > +++ b/hw/arm/aspeed_ast27x0.c
> > @@ -1260,7 +1260,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
> > sc->macs_num = 3;
> > sc->uarts_num = 13;
> > sc->num_cpus = 4;
> > - sc->ioexp_num = 0;
> > + sc->ioexp_num = 2;
> > sc->uarts_base = ASPEED_DEV_UART0;
> > sc->irqmap = aspeed_soc_ast2700a1_irqmap;
> > sc->memmap = aspeed_soc_ast2700_memmap;
>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>
>
> Thanks,
>
> C.
^ permalink raw reply [flat|nested] 74+ messages in thread
* RE: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-12-29 19:35 ` Nabih Estefan
@ 2025-12-30 9:58 ` Kane Chen
2025-12-30 14:28 ` Cédric Le Goater
0 siblings, 1 reply; 74+ messages in thread
From: Kane Chen @ 2025-12-30 9:58 UTC (permalink / raw)
To: Nabih Estefan, Cédric Le Goater
Cc: Peter Maydell, Steven Lee, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Troy Lee,
Philippe Mathieu-Daudé
> -----Original Message-----
> From: Nabih Estefan <nabihestefan@google.com>
> Sent: Tuesday, December 30, 2025 3:36 AM
> To: Cédric Le Goater <clg@kaod.org>
> Cc: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>; Troy Lee <troy_lee@aspeedtech.com>;
> Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller
> for AST1700
>
> On Mon, Dec 29, 2025 at 8:51 AM Cédric Le Goater <clg@kaod.org> wrote:
> >
> > +phil
> >
> > On 12/29/25 12:41, Cédric Le Goater wrote:
> > > On 12/29/25 11:00, Kane Chen wrote:
> > >>> -----Original Message-----
> > >>> From: Cédric Le Goater <clg@kaod.org>
> > >>> Sent: Sunday, December 28, 2025 1:51 AM
> > >>> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> > >>> <peter.maydell@linaro.org>; Steven Lee
> > >>> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Jamin
> > >>> Lin <jamin_lin@aspeedtech.com>; Andrew Jeffery
> > >>> <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
> > >>> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> > >>> here <qemu-devel@nongnu.org>
> > >>> Cc: Troy Lee <troy_lee@aspeedtech.com>; nabihestefan@google.com
> > >>> Subject: Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt
> > >>> controller for AST1700
> > >>>
> > >>> Hello Kane,
> > >>>
> > >>>> Thank you for the suggestion. Since I need to submit a v5 patch
> > >>>> to split the I2C code changes anyway,
> > >>>
> > >>> Can you please introduce the bus label property at the end of the patch
> series ?
> > >>> Please consider adding a functional test and updating the documentation
> too.
> > >>>
> > >>>> I will handle the naming adjustments and other minor fixes myself
> > >>>> in that version.
> > >>>
> > >>> Thanks,
> > >>>
> > >>> C.
> > >>
> > >> Hi Cédric,
> > >>
> > >> If I move the bus label property to the end of this patch series,
> > >> it will trigger a test failure in the current patch series.
> > >
> > > Which test ?
> > >
> > >> To avoid this, I plan to move the bus label changes into a separate
> > >> patch series and submit it before the AST1700 series. I believe
> > >> this approach ensures both series pass the tests properly.
> > >> What are your thoughts on this?
> > >
> > > I would like to understand the issue first.
> > I see.
> >
> > The AST2700 functional tests fail :
> >
> > self.vm.add_args('-device',
> >
> > 'tmp105,bus=aspeed.i2c.bus.1,address=0x4d,id=tmp-test')
> >
> > The "bus label" proposal renames the IO expander I2C buses (32) to
> > avoid the name conflicts :
> >
> > /aspeed.ioexp0.i2c.bus.0 (i2c-bus)
> > ...
> > /aspeed.ioexp0.i2c.bus.15 (i2c-bus)
> >
> > /aspeed.ioexp1.i2c.bus.0 (i2c-bus)
> > ...
> > /aspeed.ioexp1.i2c.bus.15 (i2c-bus)
> >
> > Since this will be exposed in the user API, it would be best to avoid
> > introducing poorly chosen names. Having so many I2C buses (48) in a
> > single machine is somewhat new in QEMU and I am not aware of any
> > naming convention for this.
> >
> > May be others do ?
> >
> > Thanks,
> >
> > C.
>
> I'm not aware of any convention, but I'd argue the current naming with the bus
> label makes sense. A i2c bus on the main machine is "aspeed.i2c.bus.%d"
> which clearly makes it easy to differenciate but see that the two busses are
> somehow related. Maybe it'd be worth changing the `aspeed_i2c_class_init` to
> make this relation more obvious by not using TYPE_ASPEED_I2C_BUS but use
> the string explicitly?
>
> Thanks,
> Nabih
Hi Cédric,
Thanks for the additional information.
Hi all,
Currently, three devices in our setup support I2C.
1. BMC
2. IO expander 1
3. IO expander 2
Each device supports 16 I2C buses, and the bus indices for each device all start
from 0. This leads to naming conflicts under the current naming convention. While
we could extend the bus IDs from 16 to 47, doing so would require significant code
changes to handle different ID ranges, making the code harder to maintain.
Therefore, I believe using readable bus labels would be more intuitive for the user API.
If there are any existing conventions for this use case or if you have any concerns
regarding the use of bus labels, please let me know.
Best Regards,
Kane
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-12-30 9:58 ` Kane Chen
@ 2025-12-30 14:28 ` Cédric Le Goater
2025-12-31 10:15 ` Kane Chen
0 siblings, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2025-12-30 14:28 UTC (permalink / raw)
To: Kane Chen, Nabih Estefan
Cc: Peter Maydell, Steven Lee, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Troy Lee,
Philippe Mathieu-Daudé
Hello Kane,
> Currently, three devices in our setup support I2C.
> 1. BMC
> 2. IO expander 1
> 3. IO expander 2
>
> Each device supports 16 I2C buses, and the bus indices for each device all start
> from 0. This leads to naming conflicts under the current naming convention. While
> we could extend the bus IDs from 16 to 47, doing so would require significant code
> changes to handle different ID ranges, making the code harder to maintain.
>
> Therefore, I believe using readable bus labels would be more intuitive for the user API.
I tend to agree.
> If there are any existing conventions for this use case or if you have any concerns
> regarding the use of bus labels, please let me know.
Could you please send us the contents of directory :
/sys/bus/i2c/devices/
on a system with such IO expanders? preferably with some devices
attached to the I2C buses.
Thanks,
C.
^ permalink raw reply [flat|nested] 74+ messages in thread
* RE: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-12-30 14:28 ` Cédric Le Goater
@ 2025-12-31 10:15 ` Kane Chen
2025-12-31 11:49 ` Cédric Le Goater
0 siblings, 1 reply; 74+ messages in thread
From: Kane Chen @ 2025-12-31 10:15 UTC (permalink / raw)
To: Cédric Le Goater, Nabih Estefan
Cc: Peter Maydell, Steven Lee, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Troy Lee,
Philippe Mathieu-Daudé
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Tuesday, December 30, 2025 10:29 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Nabih Estefan
> <nabihestefan@google.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Jamin Lin
> <jamin_lin@aspeedtech.com>; Andrew Jeffery
> <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>; Troy Lee <troy_lee@aspeedtech.com>; Philippe
> Mathieu-Daudé <philmd@linaro.org>
> Subject: Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller
> for AST1700
>
> Hello Kane,
>
> > Currently, three devices in our setup support I2C.
> > 1. BMC
> > 2. IO expander 1
> > 3. IO expander 2
> >
> > Each device supports 16 I2C buses, and the bus indices for each device
> > all start from 0. This leads to naming conflicts under the current
> > naming convention. While we could extend the bus IDs from 16 to 47,
> > doing so would require significant code changes to handle different ID ranges,
> making the code harder to maintain.
> >
> > Therefore, I believe using readable bus labels would be more intuitive for the
> user API.
>
> I tend to agree.
>
> > If there are any existing conventions for this use case or if you have
> > any concerns regarding the use of bus labels, please let me know.
>
> Could you please send us the contents of directory :
>
> /sys/bus/i2c/devices/
>
> on a system with such IO expanders? preferably with some devices attached
> to the I2C buses.
>
> Thanks,
>
> C.
Hi Cédric,
I'm afraid I cannot provide data from a physical platform on such short notice.
Currently, my AST1700 board is malfunctioning, and our other unit is occupied
with different tests. I am reaching out to colleagues to see if a spare is available.
I've attached logs from a QEMU simulation, as the results are expected to be
consistent with the actual hardware.. Since our EVB does not have I2C devices
connected to these specific buses, I typically use the following command to
create a dummy device for testing:
echo slave-24c02 0x106c > /sys/bus/i2c/devices/i2c-16/new_device"
System info:
ls -l /sys/bus/i2c/devices/
lrwxrwxrwx 1 root root 0 Apr 3 2025 10-1010 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0fb00.i2c-bus/i2c-10/10-1010
lrwxrwxrwx 1 root root 0 Dec 31 09:43 16-106c -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f100.i2c-bus/i2c-16/16-106c
lrwxrwxrwx 1 root root 0 Apr 3 2025 8-1010 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0f900.i2c-bus/i2c-8/8-1010
lrwxrwxrwx 1 root root 0 Apr 3 2025 9-0050 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0fa00.i2c-bus/i2c-9/9-0050
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-10 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0fb00.i2c-bus/i2c-10
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-16 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f100.i2c-bus/i2c-16
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-17 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f200.i2c-bus/i2c-17
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-18 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f300.i2c-bus/i2c-18
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-19 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f400.i2c-bus/i2c-19
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-20 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f500.i2c-bus/i2c-20
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-21 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f600.i2c-bus/i2c-21
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-22 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f700.i2c-bus/i2c-22
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-23 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f800.i2c-bus/i2c-23
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-24 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f900.i2c-bus/i2c-24
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-25 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fa00.i2c-bus/i2c-25
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-26 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fb00.i2c-bus/i2c-26
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-27 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fc00.i2c-bus/i2c-27
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-28 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fd00.i2c-bus/i2c-28
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-29 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fe00.i2c-bus/i2c-29
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-30 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0ff00.i2c-bus/i2c-30
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-31 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c10000.i2c-bus/i2c-31
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-32 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f100.i2c-bus/i2c-32
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-33 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f200.i2c-bus/i2c-33
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-34 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f300.i2c-bus/i2c-34
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-35 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f400.i2c-bus/i2c-35
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-36 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f500.i2c-bus/i2c-36
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-37 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f600.i2c-bus/i2c-37
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-38 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f700.i2c-bus/i2c-38
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-39 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f800.i2c-bus/i2c-39
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-40 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f900.i2c-bus/i2c-40
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-41 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fa00.i2c-bus/i2c-41
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-42 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fb00.i2c-bus/i2c-42
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-43 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fc00.i2c-bus/i2c-43
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-44 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fd00.i2c-bus/i2c-44
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-45 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fe00.i2c-bus/i2c-45
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-46 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0ff00.i2c-bus/i2c-46
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-47 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c10000.i2c-bus/i2c-47
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-8 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0f900.i2c-bus/i2c-8
lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-9 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0fa00.i2c-bus/i2c-9
Best Regards,
Kane
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-12-31 10:15 ` Kane Chen
@ 2025-12-31 11:49 ` Cédric Le Goater
2026-01-02 16:31 ` Cédric Le Goater
0 siblings, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2025-12-31 11:49 UTC (permalink / raw)
To: Kane Chen, Nabih Estefan
Cc: Peter Maydell, Steven Lee, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Troy Lee,
Philippe Mathieu-Daudé
Hello Kane,
On 12/31/25 11:15, Kane Chen wrote:
>> -----Original Message-----
>> From: Cédric Le Goater <clg@kaod.org>
>> Sent: Tuesday, December 30, 2025 10:29 PM
>> To: Kane Chen <kane_chen@aspeedtech.com>; Nabih Estefan
>> <nabihestefan@google.com>
>> Cc: Peter Maydell <peter.maydell@linaro.org>; Steven Lee
>> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Jamin Lin
>> <jamin_lin@aspeedtech.com>; Andrew Jeffery
>> <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
>> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
>> <qemu-devel@nongnu.org>; Troy Lee <troy_lee@aspeedtech.com>; Philippe
>> Mathieu-Daudé <philmd@linaro.org>
>> Subject: Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller
>> for AST1700
>>
>> Hello Kane,
>>
>>> Currently, three devices in our setup support I2C.
>>> 1. BMC
>>> 2. IO expander 1
>>> 3. IO expander 2
>>>
>>> Each device supports 16 I2C buses, and the bus indices for each device
>>> all start from 0. This leads to naming conflicts under the current
>>> naming convention. While we could extend the bus IDs from 16 to 47,
>>> doing so would require significant code changes to handle different ID ranges,
>> making the code harder to maintain.
>>>
>>> Therefore, I believe using readable bus labels would be more intuitive for the
>> user API.
>>
>> I tend to agree.
>>
>>> If there are any existing conventions for this use case or if you have
>>> any concerns regarding the use of bus labels, please let me know.
>>
>> Could you please send us the contents of directory :
>>
>> /sys/bus/i2c/devices/
>>
>> on a system with such IO expanders? preferably with some devices attached
>> to the I2C buses.
>>
>> Thanks,
>>
>> C.
>
> Hi Cédric,
>
> I'm afraid I cannot provide data from a physical platform on such short notice.
> Currently, my AST1700 board is malfunctioning, and our other unit is occupied
> with different tests. I am reaching out to colleagues to see if a spare is available.
>
> I've attached logs from a QEMU simulation, as the results are expected to be
> consistent with the actual hardware.. Since our EVB does not have I2C devices
> connected to these specific buses, I typically use the following command to
> create a dummy device for testing:
> echo slave-24c02 0x106c > /sys/bus/i2c/devices/i2c-16/new_device"
Which command line did you use for the I2C backing device in QEMU ?
Is there a specific FW image to use to enable the IO expanders ?
> System info:
> ls -l /sys/bus/i2c/devices/
> lrwxrwxrwx 1 root root 0 Apr 3 2025 10-1010 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0fb00.i2c-bus/i2c-10/10-1010
> lrwxrwxrwx 1 root root 0 Dec 31 09:43 16-106c -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f100.i2c-bus/i2c-16/16-106c
> lrwxrwxrwx 1 root root 0 Apr 3 2025 8-1010 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0f900.i2c-bus/i2c-8/8-1010
> lrwxrwxrwx 1 root root 0 Apr 3 2025 9-0050 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0fa00.i2c-bus/i2c-9/9-0050
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-10 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0fb00.i2c-bus/i2c-10
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-16 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f100.i2c-bus/i2c-16
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-17 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f200.i2c-bus/i2c-17
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-18 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f300.i2c-bus/i2c-18
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-19 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f400.i2c-bus/i2c-19
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-20 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f500.i2c-bus/i2c-20
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-21 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f600.i2c-bus/i2c-21
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-22 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f700.i2c-bus/i2c-22
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-23 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f800.i2c-bus/i2c-23
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-24 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f900.i2c-bus/i2c-24
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-25 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fa00.i2c-bus/i2c-25
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-26 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fb00.i2c-bus/i2c-26
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-27 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fc00.i2c-bus/i2c-27
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-28 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fd00.i2c-bus/i2c-28
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-29 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fe00.i2c-bus/i2c-29
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-30 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0ff00.i2c-bus/i2c-30
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-31 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c10000.i2c-bus/i2c-31
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-32 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f100.i2c-bus/i2c-32
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-33 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f200.i2c-bus/i2c-33
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-34 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f300.i2c-bus/i2c-34
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-35 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f400.i2c-bus/i2c-35
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-36 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f500.i2c-bus/i2c-36
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-37 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f600.i2c-bus/i2c-37
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-38 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f700.i2c-bus/i2c-38
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-39 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f800.i2c-bus/i2c-39
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-40 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f900.i2c-bus/i2c-40
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-41 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fa00.i2c-bus/i2c-41
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-42 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fb00.i2c-bus/i2c-42
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-43 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fc00.i2c-bus/i2c-43
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-44 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fd00.i2c-bus/i2c-44
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-45 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fe00.i2c-bus/i2c-45
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-46 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0ff00.i2c-bus/i2c-46
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-47 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c10000.i2c-bus/i2c-47
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-8 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0f900.i2c-bus/i2c-8
> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-9 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0fa00.i2c-bus/i2c-9
Could we order the I2C buses the same way in QEMU ?
Thanks,
C.
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2025-12-31 11:49 ` Cédric Le Goater
@ 2026-01-02 16:31 ` Cédric Le Goater
2026-01-05 9:51 ` Kane Chen
0 siblings, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2026-01-02 16:31 UTC (permalink / raw)
To: Kane Chen, Nabih Estefan
Cc: Peter Maydell, Steven Lee, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Troy Lee,
Philippe Mathieu-Daudé
On 12/31/25 12:49, Cédric Le Goater wrote:
> Hello Kane,
>
> On 12/31/25 11:15, Kane Chen wrote:
>>> -----Original Message-----
>>> From: Cédric Le Goater <clg@kaod.org>
>>> Sent: Tuesday, December 30, 2025 10:29 PM
>>> To: Kane Chen <kane_chen@aspeedtech.com>; Nabih Estefan
>>> <nabihestefan@google.com>
>>> Cc: Peter Maydell <peter.maydell@linaro.org>; Steven Lee
>>> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Jamin Lin
>>> <jamin_lin@aspeedtech.com>; Andrew Jeffery
>>> <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
>>> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
>>> <qemu-devel@nongnu.org>; Troy Lee <troy_lee@aspeedtech.com>; Philippe
>>> Mathieu-Daudé <philmd@linaro.org>
>>> Subject: Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller
>>> for AST1700
>>>
>>> Hello Kane,
>>>
>>>> Currently, three devices in our setup support I2C.
>>>> 1. BMC
>>>> 2. IO expander 1
>>>> 3. IO expander 2
>>>>
>>>> Each device supports 16 I2C buses, and the bus indices for each device
>>>> all start from 0. This leads to naming conflicts under the current
>>>> naming convention. While we could extend the bus IDs from 16 to 47,
>>>> doing so would require significant code changes to handle different ID ranges,
>>> making the code harder to maintain.
>>>>
>>>> Therefore, I believe using readable bus labels would be more intuitive for the
>>> user API.
>>>
>>> I tend to agree.
>>>
>>>> If there are any existing conventions for this use case or if you have
>>>> any concerns regarding the use of bus labels, please let me know.
>>>
>>> Could you please send us the contents of directory :
>>>
>>> /sys/bus/i2c/devices/
>>>
>>> on a system with such IO expanders? preferably with some devices attached
>>> to the I2C buses.
>>>
>>> Thanks,
>>>
>>> C.
>>
>> Hi Cédric,
>>
>> I'm afraid I cannot provide data from a physical platform on such short notice.
>> Currently, my AST1700 board is malfunctioning, and our other unit is occupied
>> with different tests. I am reaching out to colleagues to see if a spare is available.
>>
>> I've attached logs from a QEMU simulation, as the results are expected to be
>> consistent with the actual hardware.. Since our EVB does not have I2C devices
>> connected to these specific buses, I typically use the following command to
>> create a dummy device for testing:
>> echo slave-24c02 0x106c > /sys/bus/i2c/devices/i2c-16/new_device"
>
> Which command line did you use for the I2C backing device in QEMU ?
>
> Is there a specific FW image to use to enable the IO expanders ?
>
>> System info:
>> ls -l /sys/bus/i2c/devices/
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 10-1010 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0fb00.i2c-bus/i2c-10/10-1010
>> lrwxrwxrwx 1 root root 0 Dec 31 09:43 16-106c -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f100.i2c-bus/i2c-16/16-106c
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 8-1010 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0f900.i2c-bus/i2c-8/8-1010
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 9-0050 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0fa00.i2c-bus/i2c-9/9-0050
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-10 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0fb00.i2c-bus/i2c-10
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-16 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f100.i2c-bus/i2c-16
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-17 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f200.i2c-bus/i2c-17
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-18 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f300.i2c-bus/i2c-18
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-19 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f400.i2c-bus/i2c-19
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-20 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f500.i2c-bus/i2c-20
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-21 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f600.i2c-bus/i2c-21
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-22 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f700.i2c-bus/i2c-22
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-23 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f800.i2c-bus/i2c-23
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-24 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f900.i2c-bus/i2c-24
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-25 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fa00.i2c-bus/i2c-25
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-26 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fb00.i2c-bus/i2c-26
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-27 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fc00.i2c-bus/i2c-27
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-28 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fd00.i2c-bus/i2c-28
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-29 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fe00.i2c-bus/i2c-29
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-30 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0ff00.i2c-bus/i2c-30
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-31 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c10000.i2c-bus/i2c-31
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-32 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f100.i2c-bus/i2c-32
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-33 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f200.i2c-bus/i2c-33
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-34 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f300.i2c-bus/i2c-34
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-35 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f400.i2c-bus/i2c-35
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-36 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f500.i2c-bus/i2c-36
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-37 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f600.i2c-bus/i2c-37
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-38 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f700.i2c-bus/i2c-38
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-39 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f800.i2c-bus/i2c-39
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-40 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f900.i2c-bus/i2c-40
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-41 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fa00.i2c-bus/i2c-41
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-42 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fb00.i2c-bus/i2c-42
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-43 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fc00.i2c-bus/i2c-43
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-44 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fd00.i2c-bus/i2c-44
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-45 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fe00.i2c-bus/i2c-45
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-46 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0ff00.i2c-bus/i2c-46
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-47 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c10000.i2c-bus/i2c-47
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-8 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0f900.i2c-bus/i2c-8
>> lrwxrwxrwx 1 root root 0 Apr 3 2025 i2c-9 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0fa00.i2c-bus/i2c-9
>
> Could we order the I2C buses the same way in QEMU ?
We would need to modify the bus creation in aspeed_i2c_bus_realize()
as follows :
s->bus = i2c_init_bus(dev, NULL);
and fix all tests.
Hmm, I am pondering the possible solutions.
C.
^ permalink raw reply [flat|nested] 74+ messages in thread
* RE: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2026-01-02 16:31 ` Cédric Le Goater
@ 2026-01-05 9:51 ` Kane Chen
2026-01-05 11:18 ` Cédric Le Goater
0 siblings, 1 reply; 74+ messages in thread
From: Kane Chen @ 2026-01-05 9:51 UTC (permalink / raw)
To: Cédric Le Goater, Nabih Estefan
Cc: Peter Maydell, Steven Lee, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Troy Lee,
Philippe Mathieu-Daudé
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Saturday, January 3, 2026 12:32 AM
> To: Kane Chen <kane_chen@aspeedtech.com>; Nabih Estefan
> <nabihestefan@google.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Jamin Lin
> <jamin_lin@aspeedtech.com>; Andrew Jeffery
> <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>; Troy Lee <troy_lee@aspeedtech.com>; Philippe
> Mathieu-Daudé <philmd@linaro.org>
> Subject: Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller
> for AST1700
>
> On 12/31/25 12:49, Cédric Le Goater wrote:
> > Hello Kane,
> >
> > On 12/31/25 11:15, Kane Chen wrote:
> >>> -----Original Message-----
> >>> From: Cédric Le Goater <clg@kaod.org>
> >>> Sent: Tuesday, December 30, 2025 10:29 PM
> >>> To: Kane Chen <kane_chen@aspeedtech.com>; Nabih Estefan
> >>> <nabihestefan@google.com>
> >>> Cc: Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> >>> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Jamin
> Lin
> >>> <jamin_lin@aspeedtech.com>; Andrew Jeffery
> >>> <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
> >>> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> >>> here <qemu-devel@nongnu.org>; Troy Lee <troy_lee@aspeedtech.com>;
> >>> Philippe Mathieu-Daudé <philmd@linaro.org>
> >>> Subject: Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt
> >>> controller for AST1700
> >>>
> >>> Hello Kane,
> >>>
> >>>> Currently, three devices in our setup support I2C.
> >>>> 1. BMC
> >>>> 2. IO expander 1
> >>>> 3. IO expander 2
> >>>>
> >>>> Each device supports 16 I2C buses, and the bus indices for each
> >>>> device all start from 0. This leads to naming conflicts under the
> >>>> current naming convention. While we could extend the bus IDs from
> >>>> 16 to 47, doing so would require significant code changes to handle
> >>>> different ID ranges,
> >>> making the code harder to maintain.
> >>>>
> >>>> Therefore, I believe using readable bus labels would be more
> >>>> intuitive for the
> >>> user API.
> >>>
> >>> I tend to agree.
> >>>
> >>>> If there are any existing conventions for this use case or if you
> >>>> have any concerns regarding the use of bus labels, please let me know.
> >>>
> >>> Could you please send us the contents of directory :
> >>>
> >>> /sys/bus/i2c/devices/
> >>>
> >>> on a system with such IO expanders? preferably with some devices
> >>> attached to the I2C buses.
> >>>
> >>> Thanks,
> >>>
> >>> C.
> >>
> >> Hi Cédric,
> >>
> >> I'm afraid I cannot provide data from a physical platform on such short
> notice.
> >> Currently, my AST1700 board is malfunctioning, and our other unit is
> >> occupied with different tests. I am reaching out to colleagues to see if a
> spare is available.
> >>
> >> I've attached logs from a QEMU simulation, as the results are
> >> expected to be consistent with the actual hardware.. Since our EVB
> >> does not have I2C devices connected to these specific buses, I
> >> typically use the following command to create a dummy device for testing:
> >> echo slave-24c02 0x106c > /sys/bus/i2c/devices/i2c-16/new_device"
> >
> > Which command line did you use for the I2C backing device in QEMU ?
I used the following command to test the LTPI feature.
Note that no additional options were added specifically for the I2C devices;
I am relying on the default machine model configuration:
./qemu-system-aarch64 -M ast2700a1-evb -nographic \
-device loader,addr=0x400000000,file=2700-img/u-boot.bin,force-raw=on \
-device loader,addr=0x430000000,file=2700-img/bl31.bin,force-raw=on \
-device loader,addr=0x430080000,file=2700-img/optee/tee-raw.bin,force-raw=on \
-device loader,addr=0x430000000,cpu-num=0 \
-device loader,addr=0x430000000,cpu-num=1 \
-device loader,addr=0x430000000,cpu-num=2 \
-device loader,addr=0x430000000,cpu-num=3 \
-drive file=2700-img/image-bmc,format=raw,if=mtd \
-net nic,macaddr=32:27:a1:12:01:01 \
-net nic,macaddr=32:27:a1:12:02:02 \
-net nic,macaddr=32:27:a1:12:03:03 \
-net user,hostfwd=:127.0.0.1:12222-:22,hostfwd=:127.0.0.1:12443-:443,hostfwd=udp:127.0.0.1:12623-:623,hostname=qemu \
-serial mon:stdio
> >
> > Is there a specific FW image to use to enable the IO expanders ?
To enable the IO expanders, users could use the below DTS file to build the image
https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/ast2700-dcscm_ast1700-evb.dts
Or user could use the below image and switch the DTB in the uboot stage for enabling
IO expanders.
https://github.com/AspeedTech-BMC/openbmc/releases/download/v10.00/ast2700-a1-dcscm-obmc.tar.gz
> >
> >> System info:
> >> ls -l /sys/bus/i2c/devices/
> >> lrwxrwxrwx 1 root root 0 Apr 3 2025
> 10-1010 ->
> >> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/1
> 4c0
> >> fb00.i2c-bus/i2c-10/10-1010 lrwxrwxrwx 1
> root root
> >> 0 Dec 31 09:43 16-106c ->
> >> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 3
> >> 0c0f000/30c0f100.i2c-bus/i2c-16/16-106c
> >> lrwxrwxrwx 1 root root 0 Apr 3 2025
> 8-1010 ->
> >> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/1
> 4c0
> >> f900.i2c-bus/i2c-8/8-1010 lrwxrwxrwx 1
> root root 0
> >> Apr 3 2025 9-0050 ->
> >> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/1
> 4c0
> >> fa00.i2c-bus/i2c-9/9-0050 lrwxrwxrwx 1
> root root 0
> >> Apr 3 2025 i2c-10 ->
> >> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/1
> 4c0
> >> fb00.i2c-bus/i2c-10 lrwxrwxrwx 1
> root root 0 Apr
> >> 3 2025 i2c-16 ->
> >> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 3
> >> 0c0f000/30c0f100.i2c-bus/i2c-16 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-17 ->
> >> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 3
> >> 0c0f000/30c0f200.i2c-bus/i2c-17 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-18 ->
> >> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 3
> >> 0c0f000/30c0f300.i2c-bus/i2c-18 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-19 ->
> >> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 3
> >> 0c0f000/30c0f400.i2c-bus/i2c-19 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-20 ->
> >> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 3
> >> 0c0f000/30c0f500.i2c-bus/i2c-20 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-21 ->
> >> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 3
> >> 0c0f000/30c0f600.i2c-bus/i2c-21 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-22 ->
> >> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 3
> >> 0c0f000/30c0f700.i2c-bus/i2c-22 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-23 ->
> >> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 3
> >> 0c0f000/30c0f800.i2c-bus/i2c-23 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-24 ->
> >> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 3
> >> 0c0f000/30c0f900.i2c-bus/i2c-24 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-25 ->
> >> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 3
> >> 0c0f000/30c0fa00.i2c-bus/i2c-25 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-26 ->
> >> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 3
> >> 0c0f000/30c0fb00.i2c-bus/i2c-26 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-27 ->
> >> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 3
> >> 0c0f000/30c0fc00.i2c-bus/i2c-27 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-28 ->
> >> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 3
> >> 0c0f000/30c0fd00.i2c-bus/i2c-28 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-29 ->
> >> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 3
> >> 0c0f000/30c0fe00.i2c-bus/i2c-29 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-30 ->
> >> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 3
> >> 0c0f000/30c0ff00.i2c-bus/i2c-30 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-31 ->
> >> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 3
> >> 0c0f000/30c10000.i2c-bus/i2c-31 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-32 ->
> >> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 5
> >> 0c0f000/50c0f100.i2c-bus/i2c-32 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-33 ->
> >> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 5
> >> 0c0f000/50c0f200.i2c-bus/i2c-33 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-34 ->
> >> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 5
> >> 0c0f000/50c0f300.i2c-bus/i2c-34 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-35 ->
> >> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 5
> >> 0c0f000/50c0f400.i2c-bus/i2c-35 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-36 ->
> >> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 5
> >> 0c0f000/50c0f500.i2c-bus/i2c-36 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-37 ->
> >> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 5
> >> 0c0f000/50c0f600.i2c-bus/i2c-37 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-38 ->
> >> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 5
> >> 0c0f000/50c0f700.i2c-bus/i2c-38 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-39 ->
> >> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 5
> >> 0c0f000/50c0f800.i2c-bus/i2c-39 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-40 ->
> >> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 5
> >> 0c0f000/50c0f900.i2c-bus/i2c-40 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-41 ->
> >> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 5
> >> 0c0f000/50c0fa00.i2c-bus/i2c-41 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-42 ->
> >> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 5
> >> 0c0f000/50c0fb00.i2c-bus/i2c-42 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-43 ->
> >> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 5
> >> 0c0f000/50c0fc00.i2c-bus/i2c-43 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-44 ->
> >> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 5
> >> 0c0f000/50c0fd00.i2c-bus/i2c-44 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-45 ->
> >> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 5
> >> 0c0f000/50c0fe00.i2c-bus/i2c-45 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-46 ->
> >> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 5
> >> 0c0f000/50c0ff00.i2c-bus/i2c-46 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-47 ->
> >> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 5
> >> 0c0f000/50c10000.i2c-bus/i2c-47 lrwxrwxrwx 1
> root root
> >> 0 Apr 3 2025 i2c-8 ->
> >> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/1
> 4c0
> >> f900.i2c-bus/i2c-8 lrwxrwxrwx 1 root root 0
> Apr 3
> >> 2025 i2c-9 ->
> >> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/1
> 4c0
> >> fa00.i2c-bus/i2c-9
> >
> > Could we order the I2C buses the same way in QEMU ?
Regarding your question about ordering the I2C buses in QEMU: if you mean
aligning the QEMU object paths with the i2c-X naming convention used in the
kernel, I believe that would be the most intuitive approach.
I was able to access a functional AST1700 platform today and captured the actual
bus states. Below is the output from the real hardware (using the same image as
my previous QEMU log):
ls -l /sys/bus/i2c/devices/
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-12 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0fd00.i2c-bus/i2c-12
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-13 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0fe00.i2c-bus/i2c-13
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-16 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f100.i2c-bus/i2c-16
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-17 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f200.i2c-bus/i2c-17
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-18 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f300.i2c-bus/i2c-18
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-19 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f400.i2c-bus/i2c-19
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-20 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f500.i2c-bus/i2c-20
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-21 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f600.i2c-bus/i2c-21
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-22 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f700.i2c-bus/i2c-22
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-23 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f800.i2c-bus/i2c-23
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-24 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f900.i2c-bus/i2c-24
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-25 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fa00.i2c-bus/i2c-25
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-26 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fb00.i2c-bus/i2c-26
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-27 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fc00.i2c-bus/i2c-27
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-28 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fd00.i2c-bus/i2c-28
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-29 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fe00.i2c-bus/i2c-29
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-30 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0ff00.i2c-bus/i2c-30
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-31 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c10000.i2c-bus/i2c-31
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-32 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f100.i2c-bus/i2c-32
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-33 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f200.i2c-bus/i2c-33
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-34 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f300.i2c-bus/i2c-34
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-35 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f400.i2c-bus/i2c-35
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-36 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f500.i2c-bus/i2c-36
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-37 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f600.i2c-bus/i2c-37
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-38 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f700.i2c-bus/i2c-38
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-39 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f800.i2c-bus/i2c-39
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-40 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f900.i2c-bus/i2c-40
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-41 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fa00.i2c-bus/i2c-41
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-42 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fb00.i2c-bus/i2c-42
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-43 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fc00.i2c-bus/i2c-43
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-44 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fd00.i2c-bus/i2c-44
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-45 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fe00.i2c-bus/i2c-45
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-46 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0ff00.i2c-bus/i2c-46
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-47 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c10000.i2c-bus/i2c-47
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-48 -> ../../../devices/platform/soc@14000000/14c21000.i3c1/i2c-48
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-49 -> ../../../devices/platform/soc@14000000/14c23000.i3c3/i2c-49
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-50 -> ../../../devices/platform/soc@14000000/14c25000.i3c5/i2c-50
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-51 -> ../../../devices/platform/soc@14000000/14c27000.i3c7/i2c-51
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-52 -> ../../../devices/platform/soc@14000000/14c29000.i3c9/i2c-52
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-53 -> ../../../devices/platform/soc@14000000/14c2b000.i3c11/i2c-53
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-54 -> ../../../devices/platform/soc@14000000/14c2d000.i3c13/i2c-54
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-55 -> ../../../devices/platform/soc@14000000/14c2f000.i3c15/i2c-55
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-56 -> ../../../devices/platform/ltpi0_bus@30000000/30c21000.i3c1/i2c-56
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-57 -> ../../../devices/platform/ltpi0_bus@30000000/30c23000.i3c3/i2c-57
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-58 -> ../../../devices/platform/ltpi0_bus@30000000/30c25000.i3c5/i2c-58
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-59 -> ../../../devices/platform/ltpi0_bus@30000000/30c27000.i3c7/i2c-59
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-60 -> ../../../devices/platform/ltpi0_bus@30000000/30c29000.i3c9/i2c-60
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-61 -> ../../../devices/platform/ltpi0_bus@30000000/30c2b000.i3c11/i2c-61
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-62 -> ../../../devices/platform/ltpi0_bus@30000000/30c2d000.i3c13/i2c-62
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-63 -> ../../../devices/platform/ltpi0_bus@30000000/30c2f000.i3c15/i2c-63
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-64 -> ../../../devices/platform/ltpi1_bus@50000000/50c21000.i3c1/i2c-64
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-65 -> ../../../devices/platform/ltpi1_bus@50000000/50c23000.i3c3/i2c-65
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-66 -> ../../../devices/platform/ltpi1_bus@50000000/50c25000.i3c5/i2c-66
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-67 -> ../../../devices/platform/ltpi1_bus@50000000/50c27000.i3c7/i2c-67
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-68 -> ../../../devices/platform/ltpi1_bus@50000000/50c29000.i3c9/i2c-68
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-69 -> ../../../devices/platform/ltpi1_bus@50000000/50c2b000.i3c11/i2c-69
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-70 -> ../../../devices/platform/ltpi1_bus@50000000/50c2d000.i3c13/i2c-70
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-71 -> ../../../devices/platform/ltpi1_bus@50000000/50c2f000.i3c15/i2c-71
lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-8 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0f900.i2c-bus/i2c-8
As shown above, the real platform incorporates I2C buses via the LTPI (IO expander)
and even through I3C controllers. Using a consistent i2c-X naming style across the
model should sufficiently cover these use cases.
>
> We would need to modify the bus creation in aspeed_i2c_bus_realize() as
> follows :
>
> s->bus = i2c_init_bus(dev, NULL);
>
> and fix all tests.
Regarding your suggestion to modify aspeed_i2c_bus_realize() by passing NULL as
the second argument to i2c_init_bus():
I have tested this change. It results in the following object hierarchy:
BMC I2C: /i2c/bus[0]/i2c-bus.0
IOEXP0 (LTPI0): /ioexp[0]/ioexp-i2c[0]/bus[0]/i2c-bus.16
IOEXP1 (LTPI1): /ioexp[1]/ioexp-i2c[0]/bus[0]/i2c-bus.32
By adjusting the I2C object names this way, the naming conflicts are resolved, and
the automated tests now pass correctly.
Does this structure look acceptable to you, or would you prefer a different approach
to bus indexing?
>
> Hmm, I am pondering the possible solutions.
>
> C.
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2026-01-05 9:51 ` Kane Chen
@ 2026-01-05 11:18 ` Cédric Le Goater
2026-01-06 5:45 ` Kane Chen
0 siblings, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2026-01-05 11:18 UTC (permalink / raw)
To: Kane Chen, Nabih Estefan
Cc: Peter Maydell, Steven Lee, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Troy Lee,
Philippe Mathieu-Daudé, Joe Komlodi
Hello Kane,
+ Joe (for I3C)
> I was able to access a functional AST1700 platform today and captured the actual
> bus states. Below is the output from the real hardware (using the same image as
> my previous QEMU log):
>
> ls -l /sys/bus/i2c/devices/
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-12 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0fd00.i2c-bus/i2c-12
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-13 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0fe00.i2c-bus/i2c-13
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-16 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f100.i2c-bus/i2c-16
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-17 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f200.i2c-bus/i2c-17
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-18 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f300.i2c-bus/i2c-18
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-19 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f400.i2c-bus/i2c-19
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-20 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f500.i2c-bus/i2c-20
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-21 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f600.i2c-bus/i2c-21
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-22 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f700.i2c-bus/i2c-22
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-23 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f800.i2c-bus/i2c-23
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-24 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0f900.i2c-bus/i2c-24
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-25 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fa00.i2c-bus/i2c-25
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-26 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fb00.i2c-bus/i2c-26
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-27 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fc00.i2c-bus/i2c-27
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-28 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fd00.i2c-bus/i2c-28
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-29 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0fe00.i2c-bus/i2c-29
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-30 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c0ff00.i2c-bus/i2c-30
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-31 -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@30c0f000/30c10000.i2c-bus/i2c-31
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-32 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f100.i2c-bus/i2c-32
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-33 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f200.i2c-bus/i2c-33
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-34 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f300.i2c-bus/i2c-34
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-35 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f400.i2c-bus/i2c-35
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-36 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f500.i2c-bus/i2c-36
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-37 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f600.i2c-bus/i2c-37
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-38 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f700.i2c-bus/i2c-38
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-39 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f800.i2c-bus/i2c-39
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-40 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0f900.i2c-bus/i2c-40
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-41 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fa00.i2c-bus/i2c-41
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-42 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fb00.i2c-bus/i2c-42
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-43 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fc00.i2c-bus/i2c-43
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-44 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fd00.i2c-bus/i2c-44
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-45 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0fe00.i2c-bus/i2c-45
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-46 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c0ff00.i2c-bus/i2c-46
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-47 -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@50c0f000/50c10000.i2c-bus/i2c-47
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-48 -> ../../../devices/platform/soc@14000000/14c21000.i3c1/i2c-48
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-49 -> ../../../devices/platform/soc@14000000/14c23000.i3c3/i2c-49
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-50 -> ../../../devices/platform/soc@14000000/14c25000.i3c5/i2c-50
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-51 -> ../../../devices/platform/soc@14000000/14c27000.i3c7/i2c-51
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-52 -> ../../../devices/platform/soc@14000000/14c29000.i3c9/i2c-52
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-53 -> ../../../devices/platform/soc@14000000/14c2b000.i3c11/i2c-53
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-54 -> ../../../devices/platform/soc@14000000/14c2d000.i3c13/i2c-54
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-55 -> ../../../devices/platform/soc@14000000/14c2f000.i3c15/i2c-55
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-56 -> ../../../devices/platform/ltpi0_bus@30000000/30c21000.i3c1/i2c-56
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-57 -> ../../../devices/platform/ltpi0_bus@30000000/30c23000.i3c3/i2c-57
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-58 -> ../../../devices/platform/ltpi0_bus@30000000/30c25000.i3c5/i2c-58
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-59 -> ../../../devices/platform/ltpi0_bus@30000000/30c27000.i3c7/i2c-59
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-60 -> ../../../devices/platform/ltpi0_bus@30000000/30c29000.i3c9/i2c-60
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-61 -> ../../../devices/platform/ltpi0_bus@30000000/30c2b000.i3c11/i2c-61
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-62 -> ../../../devices/platform/ltpi0_bus@30000000/30c2d000.i3c13/i2c-62
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-63 -> ../../../devices/platform/ltpi0_bus@30000000/30c2f000.i3c15/i2c-63
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-64 -> ../../../devices/platform/ltpi1_bus@50000000/50c21000.i3c1/i2c-64
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-65 -> ../../../devices/platform/ltpi1_bus@50000000/50c23000.i3c3/i2c-65
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-66 -> ../../../devices/platform/ltpi1_bus@50000000/50c25000.i3c5/i2c-66
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-67 -> ../../../devices/platform/ltpi1_bus@50000000/50c27000.i3c7/i2c-67
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-68 -> ../../../devices/platform/ltpi1_bus@50000000/50c29000.i3c9/i2c-68
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-69 -> ../../../devices/platform/ltpi1_bus@50000000/50c2b000.i3c11/i2c-69
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-70 -> ../../../devices/platform/ltpi1_bus@50000000/50c2d000.i3c13/i2c-70
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-71 -> ../../../devices/platform/ltpi1_bus@50000000/50c2f000.i3c15/i2c-71
> lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-8 -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/14c0f900.i2c-bus/i2c-8
>
> As shown above, the real platform incorporates I2C buses via the LTPI (IO expander)
> and even through I3C controllers. Using a consistent i2c-X naming style across the
> model should sufficiently cover these use cases.
>
>>
>> We would need to modify the bus creation in aspeed_i2c_bus_realize() as
>> follows :
>>
>> s->bus = i2c_init_bus(dev, NULL);
>>
>> and fix all tests.
>
> Regarding your suggestion to modify aspeed_i2c_bus_realize() by passing NULL as
> the second argument to i2c_init_bus():
> I have tested this change. It results in the following object hierarchy:
>
> BMC I2C: /i2c/bus[0]/i2c-bus.0
> IOEXP0 (LTPI0): /ioexp[0]/ioexp-i2c[0]/bus[0]/i2c-bus.16
> IOEXP1 (LTPI1): /ioexp[1]/ioexp-i2c[0]/bus[0]/i2c-bus.32
>
> By adjusting the I2C object names this way, the naming conflicts are resolved, and
> the automated tests now pass correctly.
Linux doesn’t order the I2C buses in a logical or physical sense. It numbers
them dynamically as adapters are registered. The I3C device will add another
group (SOC, LTPI0, LTP1, I3C) of I2C buses and devices.
So, we need to find a way to distinguish these groups at the QEMU machine
level to add devices on the right bus. Adding a "label" to the I2C bus model
seems to be a step in the right direction. The idea needs time to mature.
Insights are welcome.
Thanks,
C.
^ permalink raw reply [flat|nested] 74+ messages in thread
* RE: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700
2026-01-05 11:18 ` Cédric Le Goater
@ 2026-01-06 5:45 ` Kane Chen
0 siblings, 0 replies; 74+ messages in thread
From: Kane Chen @ 2026-01-06 5:45 UTC (permalink / raw)
To: Cédric Le Goater, Nabih Estefan
Cc: Peter Maydell, Steven Lee, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Troy Lee,
Philippe Mathieu-Daudé, Joe Komlodi
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Monday, January 5, 2026 7:19 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Nabih Estefan
> <nabihestefan@google.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Jamin Lin
> <jamin_lin@aspeedtech.com>; Andrew Jeffery
> <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>; Troy Lee <troy_lee@aspeedtech.com>; Philippe
> Mathieu-Daudé <philmd@linaro.org>; Joe Komlodi <komlodi@google.com>
> Subject: Re: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller
> for AST1700
>
> Hello Kane,
>
> + Joe (for I3C)
>
> > I was able to access a functional AST1700 platform today and captured
> > the actual bus states. Below is the output from the real hardware
> > (using the same image as my previous QEMU log):
> >
> > ls -l /sys/bus/i2c/devices/
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-12
> -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/1
> 4c0fd00.i2c-bus/i2c-12
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-13
> -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/1
> 4c0fe00.i2c-bus/i2c-13
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-16
> -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 30c0f000/30c0f100.i2c-bus/i2c-16
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-17
> -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 30c0f000/30c0f200.i2c-bus/i2c-17
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-18
> -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 30c0f000/30c0f300.i2c-bus/i2c-18
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-19
> -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 30c0f000/30c0f400.i2c-bus/i2c-19
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-20
> -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 30c0f000/30c0f500.i2c-bus/i2c-20
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-21
> -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 30c0f000/30c0f600.i2c-bus/i2c-21
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-22
> -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 30c0f000/30c0f700.i2c-bus/i2c-22
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-23
> -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 30c0f000/30c0f800.i2c-bus/i2c-23
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-24
> -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 30c0f000/30c0f900.i2c-bus/i2c-24
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-25
> -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 30c0f000/30c0fa00.i2c-bus/i2c-25
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-26
> -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 30c0f000/30c0fb00.i2c-bus/i2c-26
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-27
> -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 30c0f000/30c0fc00.i2c-bus/i2c-27
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-28
> -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 30c0f000/30c0fd00.i2c-bus/i2c-28
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-29
> -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 30c0f000/30c0fe00.i2c-bus/i2c-29
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-30
> -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 30c0f000/30c0ff00.i2c-bus/i2c-30
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-31
> -> ../../../devices/platform/ltpi0_bus@30000000/ltpi0_bus@30000000:bus@
> 30c0f000/30c10000.i2c-bus/i2c-31
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-32
> -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 50c0f000/50c0f100.i2c-bus/i2c-32
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-33
> -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 50c0f000/50c0f200.i2c-bus/i2c-33
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-34
> -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 50c0f000/50c0f300.i2c-bus/i2c-34
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-35
> -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 50c0f000/50c0f400.i2c-bus/i2c-35
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-36
> -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 50c0f000/50c0f500.i2c-bus/i2c-36
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-37
> -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 50c0f000/50c0f600.i2c-bus/i2c-37
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-38
> -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 50c0f000/50c0f700.i2c-bus/i2c-38
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-39
> -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 50c0f000/50c0f800.i2c-bus/i2c-39
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-40
> -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 50c0f000/50c0f900.i2c-bus/i2c-40
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-41
> -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 50c0f000/50c0fa00.i2c-bus/i2c-41
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-42
> -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 50c0f000/50c0fb00.i2c-bus/i2c-42
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-43
> -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 50c0f000/50c0fc00.i2c-bus/i2c-43
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-44
> -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 50c0f000/50c0fd00.i2c-bus/i2c-44
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-45
> -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 50c0f000/50c0fe00.i2c-bus/i2c-45
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-46
> -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 50c0f000/50c0ff00.i2c-bus/i2c-46
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-47
> -> ../../../devices/platform/ltpi1_bus@50000000/ltpi1_bus@50000000:bus@
> 50c0f000/50c10000.i2c-bus/i2c-47
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-48
> -> ../../../devices/platform/soc@14000000/14c21000.i3c1/i2c-48
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-49
> -> ../../../devices/platform/soc@14000000/14c23000.i3c3/i2c-49
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-50
> -> ../../../devices/platform/soc@14000000/14c25000.i3c5/i2c-50
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-51
> -> ../../../devices/platform/soc@14000000/14c27000.i3c7/i2c-51
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-52
> -> ../../../devices/platform/soc@14000000/14c29000.i3c9/i2c-52
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-53
> -> ../../../devices/platform/soc@14000000/14c2b000.i3c11/i2c-53
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-54
> -> ../../../devices/platform/soc@14000000/14c2d000.i3c13/i2c-54
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-55
> -> ../../../devices/platform/soc@14000000/14c2f000.i3c15/i2c-55
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-56
> -> ../../../devices/platform/ltpi0_bus@30000000/30c21000.i3c1/i2c-56
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-57
> -> ../../../devices/platform/ltpi0_bus@30000000/30c23000.i3c3/i2c-57
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-58
> -> ../../../devices/platform/ltpi0_bus@30000000/30c25000.i3c5/i2c-58
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-59
> -> ../../../devices/platform/ltpi0_bus@30000000/30c27000.i3c7/i2c-59
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-60
> -> ../../../devices/platform/ltpi0_bus@30000000/30c29000.i3c9/i2c-60
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-61
> -> ../../../devices/platform/ltpi0_bus@30000000/30c2b000.i3c11/i2c-61
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-62
> -> ../../../devices/platform/ltpi0_bus@30000000/30c2d000.i3c13/i2c-62
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-63
> -> ../../../devices/platform/ltpi0_bus@30000000/30c2f000.i3c15/i2c-63
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-64
> -> ../../../devices/platform/ltpi1_bus@50000000/50c21000.i3c1/i2c-64
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-65
> -> ../../../devices/platform/ltpi1_bus@50000000/50c23000.i3c3/i2c-65
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-66
> -> ../../../devices/platform/ltpi1_bus@50000000/50c25000.i3c5/i2c-66
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-67
> -> ../../../devices/platform/ltpi1_bus@50000000/50c27000.i3c7/i2c-67
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-68
> -> ../../../devices/platform/ltpi1_bus@50000000/50c29000.i3c9/i2c-68
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-69
> -> ../../../devices/platform/ltpi1_bus@50000000/50c2b000.i3c11/i2c-69
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-70
> -> ../../../devices/platform/ltpi1_bus@50000000/50c2d000.i3c13/i2c-70
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-71
> -> ../../../devices/platform/ltpi1_bus@50000000/50c2f000.i3c15/i2c-71
> > lrwxrwxrwx 1 root root 0 Jan 5 07:24 i2c-8
> -> ../../../devices/platform/soc@14000000/soc@14000000:bus@14c0f000/1
> 4c0f900.i2c-bus/i2c-8
> >
> > As shown above, the real platform incorporates I2C buses via the LTPI
> > (IO expander) and even through I3C controllers. Using a consistent
> > i2c-X naming style across the model should sufficiently cover these use
> cases.
> >
> >>
> >> We would need to modify the bus creation in aspeed_i2c_bus_realize()
> >> as follows :
> >>
> >> s->bus = i2c_init_bus(dev, NULL);
> >>
> >> and fix all tests.
> >
> > Regarding your suggestion to modify aspeed_i2c_bus_realize() by
> > passing NULL as the second argument to i2c_init_bus():
> > I have tested this change. It results in the following object hierarchy:
> >
> > BMC I2C: /i2c/bus[0]/i2c-bus.0
> > IOEXP0 (LTPI0): /ioexp[0]/ioexp-i2c[0]/bus[0]/i2c-bus.16
> > IOEXP1 (LTPI1): /ioexp[1]/ioexp-i2c[0]/bus[0]/i2c-bus.32
> >
> > By adjusting the I2C object names this way, the naming conflicts are
> > resolved, and the automated tests now pass correctly.
>
> Linux doesn’t order the I2C buses in a logical or physical sense. It numbers
> them dynamically as adapters are registered. The I3C device will add another
> group (SOC, LTPI0, LTP1, I3C) of I2C buses and devices.
>
> So, we need to find a way to distinguish these groups at the QEMU machine
> level to add devices on the right bus. Adding a "label" to the I2C bus model
> seems to be a step in the right direction. The idea needs time to mature.
> Insights are welcome.
>
> Thanks,
>
> C.
Hi Cédric,
After syncing with the I3C driver owner, I've confirmed that i2c-56 is indeed a
virtual adapter bridged via the I3C bus, as indicated by the sysfs entry:
i2c-56 -> ../../../devices/platform/ltpi0_bus@30000000/30c21000.i3c1/i2c-56
This adapter is not a standalone I2C hardware controller. It is a virtual interface
created by the I3C subsystem to forward I2C transactions to the I3C master driver,
which then processes them using I3C-native logic and interrupts. This is standard
Linux I3C framework behavior, where the virtual device is initialized via
i3c_master_i2c_adapter_init during i3c_master_register.
Given that these nodes are software-defined extensions rather than physical IP
blocks, we can likely exclude this "I3C-virtual-I2C" case from the QEMU grouping
logic. By focusing on the primary SOC and LTPI0/1 hardware groups instead, we
can significantly simplify bus identification at the machine level.
Best Regards,
Kane
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700 model
2025-12-24 1:41 ` [PATCH v4 14/19] hw/arm/aspeed: attach I2C " Kane Chen via
2025-12-24 11:04 ` Cédric Le Goater
@ 2026-01-07 14:53 ` Cédric Le Goater
2026-01-07 15:35 ` Cédric Le Goater
1 sibling, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2026-01-07 14:53 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan
Hello Kane,
I agree we need a way to distinguish the I2C buses belonging to
the Aspeed Soc from those of the Aspeed IO Expander, so devices
can be attached on the correct bus.
Let's proceed with your proposal. Below are some refinements.
[ ... ]
> --- a/hw/i2c/aspeed_i2c.c
> +++ b/hw/i2c/aspeed_i2c.c
> @@ -1261,6 +1261,7 @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
> static const Property aspeed_i2c_properties[] = {
> DEFINE_PROP_LINK("dram", AspeedI2CState, dram_mr,
> TYPE_MEMORY_REGION, MemoryRegion *),
> + DEFINE_PROP_STRING("bus-label", AspeedI2CState, bus_label),
> };
>
> static void aspeed_i2c_class_init(ObjectClass *klass, const void *data)
> @@ -1421,14 +1422,28 @@ static void aspeed_i2c_bus_realize(DeviceState *dev, Error **errp)
> {
> AspeedI2CBus *s = ASPEED_I2C_BUS(dev);
> AspeedI2CClass *aic;
> - g_autofree char *name = g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s->id);
I would prefer if you added a new property to AspeedI2CBus :
DEFINE_PROP_STRING("name", AspeedI2CBus, name),
which would be set in aspeed_i2c_realize() :
/* default value */
if (!s->bus_label) {
s->bus_label = g_strdup(TYPE_ASPEED_I2C_BUS);
}
g_autofree char *name = g_strdup_printf("%s.%d", s->bus_label, i);
if (!object_property_set_str(bus, "bus-name", name, errp)) {
return;
}
The naming should be a higher level decision, made at the SoC level.
So, aspeed_ast1700_realize() should be adjusted when the "bus-label"
property is set.
I don't think we need to keep the "aspeed.%s.i2c.bus" prefix. How about
removing "aspeed" (which is redudant anyhow on an Aspeed machine) ?
"ioexp%d.i2c.bus"
Also, in aspeed_i2c_bus_realize(), please make sure AspeedI2CBus::name
is set, like s->controller. This could be an assert too.
Thanks,
C.
> - g_autofree char *pool_name = g_strdup_printf("%s.pool", name);
> + g_autofree char *name = NULL;
> + g_autofree char *pool_name = NULL;
>
> if (!s->controller) {
> error_setg(errp, TYPE_ASPEED_I2C_BUS ": 'controller' link not set");
> return;
> }
>
> + /*
> + * I2C bus naming:
> + * - Empty bus_label -> BMC internal controller, use default name.
> + * - Non-empty bus_label -> external/addon controller, prefix with label
> + * to avoid conflicts and show bus origin.
> + */
> + if (!s->controller->bus_label || (strlen(s->controller->bus_label) == 0)) {
> + name = g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s->id);
> + } else {
> + name = g_strdup_printf("aspeed.%s.i2c.bus.%d",
> + s->controller->bus_label, s->id);
> + }
> + pool_name = g_strdup_printf("%s.pool", name);
> +
> aic = ASPEED_I2C_GET_CLASS(s->controller);
>
> sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700 model
2026-01-07 14:53 ` Cédric Le Goater
@ 2026-01-07 15:35 ` Cédric Le Goater
2026-01-08 8:53 ` Kane Chen
0 siblings, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2026-01-07 15:35 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan
On 1/7/26 15:53, Cédric Le Goater wrote:
> Hello Kane,
>
> I agree we need a way to distinguish the I2C buses belonging to
> the Aspeed Soc from those of the Aspeed IO Expander, so devices
> can be attached on the correct bus.
>
> Let's proceed with your proposal. Below are some refinements.
>
> [ ... ]
>
>> --- a/hw/i2c/aspeed_i2c.c
>> +++ b/hw/i2c/aspeed_i2c.c
>> @@ -1261,6 +1261,7 @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
>> static const Property aspeed_i2c_properties[] = {
>> DEFINE_PROP_LINK("dram", AspeedI2CState, dram_mr,
>> TYPE_MEMORY_REGION, MemoryRegion *),
>> + DEFINE_PROP_STRING("bus-label", AspeedI2CState, bus_label),
>> };
>> static void aspeed_i2c_class_init(ObjectClass *klass, const void *data)
>> @@ -1421,14 +1422,28 @@ static void aspeed_i2c_bus_realize(DeviceState *dev, Error **errp)
>> {
>> AspeedI2CBus *s = ASPEED_I2C_BUS(dev);
>> AspeedI2CClass *aic;
>> - g_autofree char *name = g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s->id);
>
>
> I would prefer if you added a new property to AspeedI2CBus :
>
> DEFINE_PROP_STRING("name", AspeedI2CBus, name),
>
> which would be set in aspeed_i2c_realize() :
>
> /* default value */
> if (!s->bus_label) {
> s->bus_label = g_strdup(TYPE_ASPEED_I2C_BUS);
> }
>
> g_autofree char *name = g_strdup_printf("%s.%d", s->bus_label, i);
>
> if (!object_property_set_str(bus, "bus-name", name, errp)) {
> return;
> }
The above changes may be included in a separate prerequisite patch.
Thanks,
C.
> The naming should be a higher level decision, made at the SoC level.
> So, aspeed_ast1700_realize() should be adjusted when the "bus-label"
> property is set.
>
> I don't think we need to keep the "aspeed.%s.i2c.bus" prefix. How about
> removing "aspeed" (which is redudant anyhow on an Aspeed machine) ?
>
> "ioexp%d.i2c.bus"
>
> Also, in aspeed_i2c_bus_realize(), please make sure AspeedI2CBus::name
> is set, like s->controller. This could be an assert too.
>
> Thanks,
>
> C.
>
>
>> - g_autofree char *pool_name = g_strdup_printf("%s.pool", name);
>> + g_autofree char *name = NULL;
>> + g_autofree char *pool_name = NULL;
>> if (!s->controller) {
>> error_setg(errp, TYPE_ASPEED_I2C_BUS ": 'controller' link not set");
>> return;
>> }
>> + /*
>> + * I2C bus naming:
>> + * - Empty bus_label -> BMC internal controller, use default name.
>> + * - Non-empty bus_label -> external/addon controller, prefix with label
>> + * to avoid conflicts and show bus origin.
>> + */
>> + if (!s->controller->bus_label || (strlen(s->controller->bus_label) == 0)) {
>> + name = g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s->id);
>> + } else {
>> + name = g_strdup_printf("aspeed.%s.i2c.bus.%d",
>> + s->controller->bus_label, s->id);
>> + }
>> + pool_name = g_strdup_printf("%s.pool", name);
>> +
>> aic = ASPEED_I2C_GET_CLASS(s->controller);
>> sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* RE: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700 model
2026-01-07 15:35 ` Cédric Le Goater
@ 2026-01-08 8:53 ` Kane Chen
2026-01-08 10:24 ` Cédric Le Goater
0 siblings, 1 reply; 74+ messages in thread
From: Kane Chen @ 2026-01-08 8:53 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, nabihestefan@google.com
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Wednesday, January 7, 2026 11:35 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; nabihestefan@google.com
> Subject: Re: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700
> model
>
> On 1/7/26 15:53, Cédric Le Goater wrote:
> > Hello Kane,
> >
> > I agree we need a way to distinguish the I2C buses belonging to the
> > Aspeed Soc from those of the Aspeed IO Expander, so devices can be
> > attached on the correct bus.
> >
> > Let's proceed with your proposal. Below are some refinements.
> >
> > [ ... ]
> >
> >> --- a/hw/i2c/aspeed_i2c.c
> >> +++ b/hw/i2c/aspeed_i2c.c
> >> @@ -1261,6 +1261,7 @@ static void aspeed_i2c_realize(DeviceState
> >> *dev, Error **errp)
> >> static const Property aspeed_i2c_properties[] = {
> >> DEFINE_PROP_LINK("dram", AspeedI2CState, dram_mr,
> >> TYPE_MEMORY_REGION,
> MemoryRegion *),
> >> + DEFINE_PROP_STRING("bus-label", AspeedI2CState, bus_label),
> >> };
> >> static void aspeed_i2c_class_init(ObjectClass *klass, const void
> >> *data) @@ -1421,14 +1422,28 @@ static void
> >> aspeed_i2c_bus_realize(DeviceState *dev, Error **errp)
> >> {
> >> AspeedI2CBus *s = ASPEED_I2C_BUS(dev);
> >> AspeedI2CClass *aic;
> >> - g_autofree char *name = g_strdup_printf(TYPE_ASPEED_I2C_BUS
> >> ".%d", s->id);
> >
> >
> > I would prefer if you added a new property to AspeedI2CBus :
> >
> > DEFINE_PROP_STRING("name", AspeedI2CBus, name),
> >
> > which would be set in aspeed_i2c_realize() :
> >
> > /* default value */
> > if (!s->bus_label) {
> > s->bus_label = g_strdup(TYPE_ASPEED_I2C_BUS);
> > }
> >
> > g_autofree char *name = g_strdup_printf("%s.%d", s->bus_label,
> > i);
> >
> > if (!object_property_set_str(bus, "bus-name", name, errp)) {
> > return;
> > }
>
> The above changes may be included in a separate prerequisite patch.
>
> Thanks,
>
> C.
>
>
> > The naming should be a higher level decision, made at the SoC level.
> > So, aspeed_ast1700_realize() should be adjusted when the "bus-label"
> > property is set.
> >
> > I don't think we need to keep the "aspeed.%s.i2c.bus" prefix. How
> > about removing "aspeed" (which is redudant anyhow on an Aspeed
> machine) ?
> >
> > "ioexp%d.i2c.bus"
> >
> > Also, in aspeed_i2c_bus_realize(), please make sure AspeedI2CBus::name
> > is set, like s->controller. This could be an assert too.
> >
> > Thanks,
> >
> > C.
> >
> >
> >> - g_autofree char *pool_name = g_strdup_printf("%s.pool", name);
> >> + g_autofree char *name = NULL;
> >> + g_autofree char *pool_name = NULL;
> >> if (!s->controller) {
> >> error_setg(errp, TYPE_ASPEED_I2C_BUS ": 'controller' link
> >> not set");
> >> return;
> >> }
> >> + /*
> >> + * I2C bus naming:
> >> + * - Empty bus_label -> BMC internal controller, use default
> name.
> >> + * - Non-empty bus_label -> external/addon controller, prefix
> >> +with label
> >> + * to avoid conflicts and show bus origin.
> >> + */
> >> + if (!s->controller->bus_label ||
> >> +(strlen(s->controller->bus_label) == 0)) {
> >> + name = g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s->id);
> >> + } else {
> >> + name = g_strdup_printf("aspeed.%s.i2c.bus.%d",
> >> + s->controller->bus_label,
> s->id);
> >> + }
> >> + pool_name = g_strdup_printf("%s.pool", name);
> >> +
> >> aic = ASPEED_I2C_GET_CLASS(s->controller);
> >> sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
> >
Hi Cédric,
Thanks for your suggestions. I have refactored the bus naming logic to align with
your comments. The decision making for the bus name has been moved up to the
SoC level, and the redundant "aspeed" prefix has been removed.
Here is a summary of the changes:
1. Added a bus-label property to AspeedAST1700SoCState. This allows the top-level
SoC (e.g., AST2700) to define the label during its initialization or realize phase.
2. The bus-label is passed from aspeed_ast1700_realize to the I2C controller
(AspeedI2CState).
3. In aspeed_i2c_realize, the controller generates unique names using the bus-label.
These names are passed to the AspeedI2CBus through a new bus-name property
during the initialization of the buses.
With these changes, the new object hierarchies and bus names are as follows:
BMC: /i2c/bus[0]/aspeed.i2c.bus.0
IOEXP0 (LTPI0): /ioexp[0]/ioexp-i2c[0]/bus[0]/ioexp0.0
IOEXP1 (LTPI1): /ioexp[1]/ioexp-i2c[0]/bus[0]/ioexp1.0
I have also verified that this naming convention does not require changes to existing
test scripts, and all functional tests passed successfully.
If you have no further concerns regarding this approach, I will submit the updated patch
series.
Best Regards,
Kane
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700 model
2026-01-08 8:53 ` Kane Chen
@ 2026-01-08 10:24 ` Cédric Le Goater
2026-01-09 1:22 ` Jamin Lin
2026-01-09 9:59 ` Kane Chen
0 siblings, 2 replies; 74+ messages in thread
From: Cédric Le Goater @ 2026-01-08 10:24 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, nabihestefan@google.com
Hi Kane,
> Thanks for your suggestions. I have refactored the bus naming logic to align with
> your comments. The decision making for the bus name has been moved up to the
> SoC level, and the redundant "aspeed" prefix has been removed.
>
> Here is a summary of the changes:
> 1. Added a bus-label property to AspeedAST1700SoCState. This allows the top-level
> SoC (e.g., AST2700) to define the label during its initialization or realize phase.
> 2. The bus-label is passed from aspeed_ast1700_realize to the I2C controller
> (AspeedI2CState).
> 3. In aspeed_i2c_realize, the controller generates unique names using the bus-label.
> These names are passed to the AspeedI2CBus through a new bus-name property
> during the initialization of the buses.
>
> With these changes, the new object hierarchies and bus names are as follows:
> BMC: /i2c/bus[0]/aspeed.i2c.bus.0
> IOEXP0 (LTPI0): /ioexp[0]/ioexp-i2c[0]/bus[0]/ioexp0.0
> IOEXP1 (LTPI1): /ioexp[1]/ioexp-i2c[0]/bus[0]/ioexp1.0
The names in the object hierarchy should not have changed, only
the bus names exposed to the user are impacted.
> I have also verified that this naming convention does not require changes to existing
> test scripts, and all functional tests passed successfully.
>
> If you have no further concerns regarding this approach, I will submit the updated patch
> series.
Please separate the bus-label change from the rest. I am expecting
a functional test case too, maybe we should update the sdk version
to v10.00 first ?
Thanks,
C.
^ permalink raw reply [flat|nested] 74+ messages in thread
* RE: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700 model
2026-01-08 10:24 ` Cédric Le Goater
@ 2026-01-09 1:22 ` Jamin Lin
2026-01-09 9:02 ` Cédric Le Goater
2026-01-09 9:59 ` Kane Chen
1 sibling, 1 reply; 74+ messages in thread
From: Jamin Lin @ 2026-01-09 1:22 UTC (permalink / raw)
To: Cédric Le Goater, Kane Chen, Peter Maydell, Steven Lee,
Troy Lee, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, nabihestefan@google.com, Hao Wu
> Subject: Re: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700
> model
>
> Hi Kane,
>
> > Thanks for your suggestions. I have refactored the bus naming logic to
> > align with your comments. The decision making for the bus name has
> > been moved up to the SoC level, and the redundant "aspeed" prefix has been
> removed.
> >
> > Here is a summary of the changes:
> > 1. Added a bus-label property to AspeedAST1700SoCState. This allows the
> top-level
> > SoC (e.g., AST2700) to define the label during its initialization or realize
> phase.
> > 2. The bus-label is passed from aspeed_ast1700_realize to the I2C controller
> > (AspeedI2CState).
> > 3. In aspeed_i2c_realize, the controller generates unique names using the
> bus-label.
> > These names are passed to the AspeedI2CBus through a new bus-name
> property
> > during the initialization of the buses.
> >
> > With these changes, the new object hierarchies and bus names are as
> follows:
> > BMC: /i2c/bus[0]/aspeed.i2c.bus.0
> > IOEXP0 (LTPI0): /ioexp[0]/ioexp-i2c[0]/bus[0]/ioexp0.0
> > IOEXP1 (LTPI1): /ioexp[1]/ioexp-i2c[0]/bus[0]/ioexp1.0
>
> The names in the object hierarchy should not have changed, only the bus
> names exposed to the user are impacted.
>
> > I have also verified that this naming convention does not require
> > changes to existing test scripts, and all functional tests passed successfully.
> >
> > If you have no further concerns regarding this approach, I will submit
> > the updated patch series.
>
> Please separate the bus-label change from the rest. I am expecting a functional
> test case too, maybe we should update the sdk version to v10.00 first ?
>
+ Hao
Hi Cédric, Nabih, Hao
ASPEED changed the boot image format starting from SDK v10.00. As a result, vbootrom can no longer boot correctly, and the manual loader command also needs to be updated.
Specifically, the U-Boot FIT image has been replaced with a legacy U-Boot raw image, so the secondary solution’s manual loader command must be adjusted accordingly.
I have created a new pull request to google/vbootrom and am currently waiting for review:
https://github.com/google/vbootrom/pull/12
I plan to update the functional test SDK v10.00 after this PR is merged.
Additionally, ASPEED will release SDK v11.00 on January 26, so I am also considering updating directly to v11.00 instead.
Nabih, Hao
Could you please help review this PR when you have time?
Thanks in advance for your help.
Jamin
> Thanks,
>
> C.
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700 model
2026-01-09 1:22 ` Jamin Lin
@ 2026-01-09 9:02 ` Cédric Le Goater
0 siblings, 0 replies; 74+ messages in thread
From: Cédric Le Goater @ 2026-01-09 9:02 UTC (permalink / raw)
To: Jamin Lin, Kane Chen, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, nabihestefan@google.com, Hao Wu
Hello Jamin,
> ASPEED changed the boot image format starting from SDK v10.00. As a result, vbootrom can no longer boot correctly, and the manual loader command also needs to be updated.
OK. See commit d63961f957ff for the update.
> Specifically, the U-Boot FIT image has been replaced with a legacy U-Boot raw image, so the secondary solution’s manual loader command must be adjusted accordingly.
>
> I have created a new pull request to google/vbootrom and am currently waiting for review:
> https://github.com/google/vbootrom/pull/12
>
> I plan to update the functional test SDK v10.00 after this PR is merged.
Sure. The functional test can come later.
> Additionally, ASPEED will release SDK v11.00 on January 26, so I am also considering updating directly to v11.00 instead.
Fine. Let's plan the updates for QEMU 11.0.
Thanks,
C.
>
> Nabih, Hao
> Could you please help review this PR when you have time?
>
> Thanks in advance for your help.
> Jamin
^ permalink raw reply [flat|nested] 74+ messages in thread
* RE: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700 model
2026-01-08 10:24 ` Cédric Le Goater
2026-01-09 1:22 ` Jamin Lin
@ 2026-01-09 9:59 ` Kane Chen
2026-01-09 13:26 ` Cédric Le Goater
1 sibling, 1 reply; 74+ messages in thread
From: Kane Chen @ 2026-01-09 9:59 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, nabihestefan@google.com
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Thursday, January 8, 2026 6:24 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; nabihestefan@google.com
> Subject: Re: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700
> model
>
> Hi Kane,
>
> > Thanks for your suggestions. I have refactored the bus naming logic to
> > align with your comments. The decision making for the bus name has
> > been moved up to the SoC level, and the redundant "aspeed" prefix has
> been removed.
> >
> > Here is a summary of the changes:
> > 1. Added a bus-label property to AspeedAST1700SoCState. This allows the
> top-level
> > SoC (e.g., AST2700) to define the label during its initialization or realize
> phase.
> > 2. The bus-label is passed from aspeed_ast1700_realize to the I2C controller
> > (AspeedI2CState).
> > 3. In aspeed_i2c_realize, the controller generates unique names using the
> bus-label.
> > These names are passed to the AspeedI2CBus through a new bus-name
> property
> > during the initialization of the buses.
> >
> > With these changes, the new object hierarchies and bus names are as
> follows:
> > BMC: /i2c/bus[0]/aspeed.i2c.bus.0
> > IOEXP0 (LTPI0): /ioexp[0]/ioexp-i2c[0]/bus[0]/ioexp0.0
> > IOEXP1 (LTPI1): /ioexp[1]/ioexp-i2c[0]/bus[0]/ioexp1.0
>
> The names in the object hierarchy should not have changed, only the bus
> names exposed to the user are impacted.
Sorry, I may not fully understand your point here, so I'd like to double-check.
From my understanding, the object hierarchy itself has not been changed, and
only the user-visible bus names are affected. Below is the current object hierarchy
without my changes:
BMC: /i2c/bus[0]/aspeed.i2c.bus.0
IOEXP0 (LTPI0): /ioexp[0]/ioexp-i2c[0]/bus[0]/aspeed.i2c.bus.0
IOEXP1 (LTPI1): /ioexp[1]/ioexp-i2c[0]/bus[0]/aspeed.i2c.bus.0
I believe this matches your comment that the object hierarchy remains the same,
while the bus naming logic is adjusted. Please let me know if you were expecting
a different result here, or if there is still something I should change.
>
> > I have also verified that this naming convention does not require
> > changes to existing test scripts, and all functional tests passed successfully.
> >
> > If you have no further concerns regarding this approach, I will submit
> > the updated patch series.
>
> Please separate the bus-label change from the rest. I am expecting a
> functional test case too, maybe we should update the sdk version to v10.00
> first ?
Regarding the functional test case: currently, our BMC releases do not enable AST1700
by default. I tested the image on other platforms instead. I noticed that the AST2700
DCSCM image includes a DTB with AST1700 enabled, but I ran into an image size issue.
On AST2700 EVB, the BMC image size is 128 MB, while on AST2700 DCSCM it is 64 MB.
This prevents directly loading the DCSCM image on the EVB. As a workaround, I concatenated
the DCSCM image twice to match the 128 MB size, which allowed the image to boot and
proceed with further testing. However, this feels like an unexpected and non-ideal
approach for testing.
Do you have any suggestions on how you would prefer this situation to be handled?
Thanks for your guidance.
>
> Thanks,
>
> C.
>
Best Regards,
Kane
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700 model
2026-01-09 9:59 ` Kane Chen
@ 2026-01-09 13:26 ` Cédric Le Goater
2026-01-12 8:30 ` Kane Chen
0 siblings, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2026-01-09 13:26 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, nabihestefan@google.com
On 1/9/26 10:59, Kane Chen wrote:
>> -----Original Message-----
>> From: Cédric Le Goater <clg@kaod.org>
>> Sent: Thursday, January 8, 2026 6:24 PM
>> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
>> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
>> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
>> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
>> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
>> here <qemu-devel@nongnu.org>
>> Cc: Troy Lee <troy_lee@aspeedtech.com>; nabihestefan@google.com
>> Subject: Re: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700
>> model
>>
>> Hi Kane,
>>
>>> Thanks for your suggestions. I have refactored the bus naming logic to
>>> align with your comments. The decision making for the bus name has
>>> been moved up to the SoC level, and the redundant "aspeed" prefix has
>> been removed.
>>>
>>> Here is a summary of the changes:
>>> 1. Added a bus-label property to AspeedAST1700SoCState. This allows the
>> top-level
>>> SoC (e.g., AST2700) to define the label during its initialization or realize
>> phase.
>>> 2. The bus-label is passed from aspeed_ast1700_realize to the I2C controller
>>> (AspeedI2CState).
>>> 3. In aspeed_i2c_realize, the controller generates unique names using the
>> bus-label.
>>> These names are passed to the AspeedI2CBus through a new bus-name
>> property
>>> during the initialization of the buses.
>>>
>>> With these changes, the new object hierarchies and bus names are as
>> follows:
>>> BMC: /i2c/bus[0]/aspeed.i2c.bus.0
>>> IOEXP0 (LTPI0): /ioexp[0]/ioexp-i2c[0]/bus[0]/ioexp0.0
>>> IOEXP1 (LTPI1): /ioexp[1]/ioexp-i2c[0]/bus[0]/ioexp1.0
>>
>> The names in the object hierarchy should not have changed, only the bus
>> names exposed to the user are impacted.
>
> Sorry, I may not fully understand your point here, so I'd like to double-check.
> From my understanding, the object hierarchy itself has not been changed, and
> only the user-visible bus names are affected. Below is the current object hierarchy
> without my changes:
>
> BMC: /i2c/bus[0]/aspeed.i2c.bus.0
> IOEXP0 (LTPI0): /ioexp[0]/ioexp-i2c[0]/bus[0]/aspeed.i2c.bus.0
> IOEXP1 (LTPI1): /ioexp[1]/ioexp-i2c[0]/bus[0]/aspeed.i2c.bus.0
ah yes. The "child<i2c-bus>" objects are really deep in the hierarchy.
I think it is fine.
>
> I believe this matches your comment that the object hierarchy remains the same,
> while the bus naming logic is adjusted. Please let me know if you were expecting
> a different result here, or if there is still something I should change.
>
>>
>>> I have also verified that this naming convention does not require
>>> changes to existing test scripts, and all functional tests passed successfully.
>>>
>>> If you have no further concerns regarding this approach, I will submit
>>> the updated patch series.
>>
>> Please separate the bus-label change from the rest. I am expecting a
>> functional test case too, maybe we should update the sdk version to v10.00
>> first ?
>
> Regarding the functional test case: currently, our BMC releases do not enable AST1700
> by default. I tested the image on other platforms instead. I noticed that the AST2700
> DCSCM image includes a DTB with AST1700 enabled, but I ran into an image size issue.
>
> On AST2700 EVB, the BMC image size is 128 MB, while on AST2700 DCSCM it is 64 MB.
> This prevents directly loading the DCSCM image on the EVB. As a workaround, I concatenated
> the DCSCM image twice to match the 128 MB size, which allowed the image to boot and
> proceed with further testing. However, this feels like an unexpected and non-ideal
> approach for testing.
Did you try using the "fmc-model" machine option ?
> Do you have any suggestions on how you would prefer this situation to be handled?
We could add a new "ast2700-dc-scm" machine too, if it make sense.
Thanks,
C.
^ permalink raw reply [flat|nested] 74+ messages in thread
* RE: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700 model
2026-01-09 13:26 ` Cédric Le Goater
@ 2026-01-12 8:30 ` Kane Chen
2026-01-12 8:48 ` Cédric Le Goater
0 siblings, 1 reply; 74+ messages in thread
From: Kane Chen @ 2026-01-12 8:30 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, nabihestefan@google.com
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Friday, January 9, 2026 9:26 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; nabihestefan@google.com
> Subject: Re: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700
> model
>
> On 1/9/26 10:59, Kane Chen wrote:
> >> -----Original Message-----
> >> From: Cédric Le Goater <clg@kaod.org>
> >> Sent: Thursday, January 8, 2026 6:24 PM
> >> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> >> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>;
> >> Troy Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>;
> >> Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley
> >> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> >> list:All patches CC here <qemu-devel@nongnu.org>
> >> Cc: Troy Lee <troy_lee@aspeedtech.com>; nabihestefan@google.com
> >> Subject: Re: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to
> >> AST1700 model
> >>
> >> Hi Kane,
> >>
> >>> Thanks for your suggestions. I have refactored the bus naming logic
> >>> to align with your comments. The decision making for the bus name
> >>> has been moved up to the SoC level, and the redundant "aspeed"
> >>> prefix has
> >> been removed.
> >>>
> >>> Here is a summary of the changes:
> >>> 1. Added a bus-label property to AspeedAST1700SoCState. This allows
> >>> the
> >> top-level
> >>> SoC (e.g., AST2700) to define the label during its
> >>> initialization or realize
> >> phase.
> >>> 2. The bus-label is passed from aspeed_ast1700_realize to the I2C
> controller
> >>> (AspeedI2CState).
> >>> 3. In aspeed_i2c_realize, the controller generates unique names
> >>> using the
> >> bus-label.
> >>> These names are passed to the AspeedI2CBus through a new
> >>> bus-name
> >> property
> >>> during the initialization of the buses.
> >>>
> >>> With these changes, the new object hierarchies and bus names are as
> >> follows:
> >>> BMC: /i2c/bus[0]/aspeed.i2c.bus.0
> >>> IOEXP0 (LTPI0): /ioexp[0]/ioexp-i2c[0]/bus[0]/ioexp0.0
> >>> IOEXP1 (LTPI1): /ioexp[1]/ioexp-i2c[0]/bus[0]/ioexp1.0
> >>
> >> The names in the object hierarchy should not have changed, only the
> >> bus names exposed to the user are impacted.
> >
> > Sorry, I may not fully understand your point here, so I'd like to double-check.
> > From my understanding, the object hierarchy itself has not been
> > changed, and only the user-visible bus names are affected. Below is
> > the current object hierarchy without my changes:
> >
> > BMC: /i2c/bus[0]/aspeed.i2c.bus.0
> > IOEXP0 (LTPI0): /ioexp[0]/ioexp-i2c[0]/bus[0]/aspeed.i2c.bus.0
> > IOEXP1 (LTPI1): /ioexp[1]/ioexp-i2c[0]/bus[0]/aspeed.i2c.bus.0
>
> ah yes. The "child<i2c-bus>" objects are really deep in the hierarchy.
> I think it is fine.
>
>
> >
> > I believe this matches your comment that the object hierarchy remains
> > the same, while the bus naming logic is adjusted. Please let me know
> > if you were expecting a different result here, or if there is still something I
> should change.
> >
> >>
> >>> I have also verified that this naming convention does not require
> >>> changes to existing test scripts, and all functional tests passed
> successfully.
> >>>
> >>> If you have no further concerns regarding this approach, I will
> >>> submit the updated patch series.
> >>
> >> Please separate the bus-label change from the rest. I am expecting a
> >> functional test case too, maybe we should update the sdk version to
> >> v10.00 first ?
> >
> > Regarding the functional test case: currently, our BMC releases do not
> > enable AST1700 by default. I tested the image on other platforms
> > instead. I noticed that the AST2700 DCSCM image includes a DTB with
> AST1700 enabled, but I ran into an image size issue.
> >
> > On AST2700 EVB, the BMC image size is 128 MB, while on AST2700 DCSCM
> it is 64 MB.
> > This prevents directly loading the DCSCM image on the EVB. As a
> > workaround, I concatenated the DCSCM image twice to match the 128 MB
> > size, which allowed the image to boot and proceed with further
> > testing. However, this feels like an unexpected and non-ideal approach for
> testing.
> Did you try using the "fmc-model" machine option ?
>
> > Do you have any suggestions on how you would prefer this situation to be
> handled?
>
> We could add a new "ast2700-dc-scm" machine too, if it make sense.
>
> Thanks,
>
> C.
Hi Cédric,
Thanks for your suggestion. After updating the fmc-model, I have successfully
loaded the AST2700 DCSCM image using the ast2700a1-evb machine type.
Regarding the I2C test case for the AST1700 (IO expander): would you prefer me
to append this to the end of the current AST1700 patch series, or should I submit
it as a separate patch series?
Best Regards,
Kane
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700 model
2026-01-12 8:30 ` Kane Chen
@ 2026-01-12 8:48 ` Cédric Le Goater
0 siblings, 0 replies; 74+ messages in thread
From: Cédric Le Goater @ 2026-01-12 8:48 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, nabihestefan@google.com
Hello Kane,
> Thanks for your suggestion. After updating the fmc-model, I have successfully
> loaded the AST2700 DCSCM image using the ast2700a1-evb machine type.
>
> Regarding the I2C test case for the AST1700 (IO expander): would you prefer me
> to append this to the end of the current AST1700 patch series, or should I submit
> it as a separate patch series?
If it is ready, please append the functional test at the end of v5.
Thanks,
C.
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
` (19 preceding siblings ...)
2025-12-29 19:37 ` [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Nabih Estefan
@ 2026-01-19 7:45 ` Cédric Le Goater
2026-01-19 7:51 ` Kane Chen
20 siblings, 1 reply; 74+ messages in thread
From: Cédric Le Goater @ 2026-01-19 7:45 UTC (permalink / raw)
To: Kane Chen, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, nabihestefan
Kane,
On 12/24/25 02:41, Kane Chen via wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
>
> Hi all,
>
> LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP DC-SCM
> 2.0 specification (see Figure 2):
> https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
>
> LTPI provides a protocol and physical interface for tunneling various
> low-speed signals between the Host Processor Module (HPM) and the
> Satellite Controller Module (SCM). In Figure 2 of the specification,
> the AST27x0 SoC (left) integrates two LTPI controllers, allowing it to
> connect to up to two AST1700 boards. On the other side, the AST1700
> consolidates HPM FPGA functions and multiple peripheral interfaces
> (GPIO, UART, I2C, I3C, etc.) onto a single board.
>
> Because the AST1700 exposes additional I/O interfaces (GPIO, I2C, I3C,
> and others), it acts as an I/O expander. Once connected over LTPI,
> the AST27x0 can control additional downstream devices through this link.
>
> This patch series is based on the SGPIO changes:
> https://patchwork.kernel.org/project/qemu-devel/patch/20251219-aspeed-sgpio-v5-1-fd5593178144@google.com/
>
> It introduces a basic LTPI controller model and wires it into the
> AST27x0 SoC. The series also adds the AST1700-specific LTPI expander
> device and incrementally connects common peripherals on the AST1700
> model. For the I3C block, which may cause kernel crashes, its MMIO
> region is modeled as an unimplemented device to reserve address space
> and make the missing functionality explicit, ensuring stable guest
> probing.
>
> In the official release images, the AST1700 functions are not included
> by default. To test the AST1700-related functionality, please include
> the following DTS files for probing:
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-ltpi0.dtsi
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-ltpi1.dtsi
>
> After including these DTS files in the BMC image, you can verify LTPI
> functionality using the following scenarios:
>
> 1. In U-Boot:
> Run the ltpi command to trigger the LTPI connection and display the
> current connection status.
> 2. In BMC Linux:
> Run i2cdetect -y <16-38> to scan and test the I2C buses exposed by
> the AST1700.
>
> Any feedback or suggestions are appreciated!
>
> Kane
Could you please resend a v5 asap ? The next quarter should be
quite buzy and I will have less time for Aspeed related matters.
Thanks,
C.
> ---
>
> ChangeLog
> ---------
> v4:
> - Add missing Signed-off-by
> - Fix checkpatch.pl warnings
> - Refine code structure
> - Enable AST1700 support only after all devices are ready
>
> v3:
> - Add PWM model
> - Integrate the SGPIO model
> - Fix I2C test case failure
> - Refine code structure
>
> v2:
> - Separate the AST1700 model into a standalone implementation
> - Refine the mechanism for assigning the AST1700 board number
>
> v1:
> - Initial version
> ---
>
> Kane-Chen-AS (19):
> hw/misc: Add LTPI controller
> hw/arm/aspeed: Attach LTPI controller to AST27X0 platform
> hw/misc: Add basic Aspeed PWM model
> hw/arm/aspeed: Add AST1700 LTPI expander device model
> hw/arm/aspeed: Integrate AST1700 device into AST27X0
> hw/arm/aspeed: Integrate interrupt controller for AST1700
> hw/arm/aspeed: Attach LTPI controller to AST1700 model
> hw/arm/aspeed: Attach UART device to AST1700 model
> hw/arm/aspeed: Attach SRAM device to AST1700 model
> hw/arm/aspeed: Attach SPI device to AST1700 model
> hw/arm/aspeed: Attach ADC device to AST1700 model
> hw/arm/aspeed: Attach SCU device to AST1700 model
> hw/arm/aspeed: Attach GPIO device to AST1700 model
> hw/arm/aspeed: attach I2C device to AST1700 model
> hw/arm/aspeed: Attach WDT device to AST1700 model
> hw/arm/aspeed: Attach PWM device to AST1700 model
> hw/arm/aspeed: Attach SGPIOM device to AST1700 model
> hw/arm/aspeed: Model AST1700 I3C block as unimplemented device
> hw/arm/aspeed: Enable AST1700 IO expander support
>
> include/hw/arm/aspeed_ast1700.h | 53 +++++++
> include/hw/arm/aspeed_soc.h | 25 ++-
> include/hw/i2c/aspeed_i2c.h | 1 +
> include/hw/intc/aspeed_intc.h | 2 +
> include/hw/misc/aspeed_ltpi.h | 33 ++++
> include/hw/misc/aspeed_pwm.h | 31 ++++
> hw/arm/aspeed_ast1700.c | 268 ++++++++++++++++++++++++++++++++
> hw/arm/aspeed_ast27x0.c | 165 ++++++++++++++++++--
> hw/i2c/aspeed_i2c.c | 19 ++-
> hw/intc/aspeed_intc.c | 60 +++++++
> hw/misc/aspeed_ltpi.c | 193 +++++++++++++++++++++++
> hw/misc/aspeed_pwm.c | 121 ++++++++++++++
> hw/arm/meson.build | 1 +
> hw/misc/meson.build | 2 +
> hw/misc/trace-events | 4 +
> 15 files changed, 959 insertions(+), 19 deletions(-)
> create mode 100644 include/hw/arm/aspeed_ast1700.h
> create mode 100644 include/hw/misc/aspeed_ltpi.h
> create mode 100644 include/hw/misc/aspeed_pwm.h
> create mode 100644 hw/arm/aspeed_ast1700.c
> create mode 100644 hw/misc/aspeed_ltpi.c
> create mode 100644 hw/misc/aspeed_pwm.c
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* RE: [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups
2026-01-19 7:45 ` Cédric Le Goater
@ 2026-01-19 7:51 ` Kane Chen
0 siblings, 0 replies; 74+ messages in thread
From: Kane Chen @ 2026-01-19 7:51 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, nabihestefan@google.com
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Monday, January 19, 2026 3:45 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; nabihestefan@google.com
> Subject: Re: [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and
> device hookups
>
> Kane,
>
> On 12/24/25 02:41, Kane Chen via wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > Hi all,
> >
> > LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP
> > DC-SCM
> > 2.0 specification (see Figure 2):
> > https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf
> >
> > LTPI provides a protocol and physical interface for tunneling various
> > low-speed signals between the Host Processor Module (HPM) and the
> > Satellite Controller Module (SCM). In Figure 2 of the specification,
> > the AST27x0 SoC (left) integrates two LTPI controllers, allowing it to
> > connect to up to two AST1700 boards. On the other side, the AST1700
> > consolidates HPM FPGA functions and multiple peripheral interfaces
> > (GPIO, UART, I2C, I3C, etc.) onto a single board.
> >
> > Because the AST1700 exposes additional I/O interfaces (GPIO, I2C, I3C,
> > and others), it acts as an I/O expander. Once connected over LTPI, the
> > AST27x0 can control additional downstream devices through this link.
> >
> > This patch series is based on the SGPIO changes:
> > https://patchwork.kernel.org/project/qemu-devel/patch/20251219-aspeed-
> > sgpio-v5-1-fd5593178144@google.com/
> >
> > It introduces a basic LTPI controller model and wires it into the
> > AST27x0 SoC. The series also adds the AST1700-specific LTPI expander
> > device and incrementally connects common peripherals on the AST1700
> > model. For the I3C block, which may cause kernel crashes, its MMIO
> > region is modeled as an unimplemented device to reserve address space
> > and make the missing functionality explicit, ensuring stable guest
> > probing.
> >
> > In the official release images, the AST1700 functions are not included
> > by default. To test the AST1700-related functionality, please include
> > the following DTS files for probing:
> >
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/a
> > rm64/boot/dts/aspeed/aspeed-ltpi0.dtsi
> >
> https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/a
> > rm64/boot/dts/aspeed/aspeed-ltpi1.dtsi
> >
> > After including these DTS files in the BMC image, you can verify LTPI
> > functionality using the following scenarios:
> >
> > 1. In U-Boot:
> > Run the ltpi command to trigger the LTPI connection and display the
> > current connection status.
> > 2. In BMC Linux:
> > Run i2cdetect -y <16-38> to scan and test the I2C buses exposed by
> > the AST1700.
> >
> > Any feedback or suggestions are appreciated!
> >
> > Kane
>
>
> Could you please resend a v5 asap ? The next quarter should be quite buzy and
> I will have less time for Aspeed related matters.
>
> Thanks,
>
> C.
Hi Cédric,
Sure, I'm working on it now and will send the v5 shortly.
Best Regards,
Kane
>
>
> > ---
> >
> > ChangeLog
> > ---------
> > v4:
> > - Add missing Signed-off-by
> > - Fix checkpatch.pl warnings
> > - Refine code structure
> > - Enable AST1700 support only after all devices are ready
> >
> > v3:
> > - Add PWM model
> > - Integrate the SGPIO model
> > - Fix I2C test case failure
> > - Refine code structure
> >
> > v2:
> > - Separate the AST1700 model into a standalone implementation
> > - Refine the mechanism for assigning the AST1700 board number
> >
> > v1:
> > - Initial version
> > ---
> >
> > Kane-Chen-AS (19):
> > hw/misc: Add LTPI controller
> > hw/arm/aspeed: Attach LTPI controller to AST27X0 platform
> > hw/misc: Add basic Aspeed PWM model
> > hw/arm/aspeed: Add AST1700 LTPI expander device model
> > hw/arm/aspeed: Integrate AST1700 device into AST27X0
> > hw/arm/aspeed: Integrate interrupt controller for AST1700
> > hw/arm/aspeed: Attach LTPI controller to AST1700 model
> > hw/arm/aspeed: Attach UART device to AST1700 model
> > hw/arm/aspeed: Attach SRAM device to AST1700 model
> > hw/arm/aspeed: Attach SPI device to AST1700 model
> > hw/arm/aspeed: Attach ADC device to AST1700 model
> > hw/arm/aspeed: Attach SCU device to AST1700 model
> > hw/arm/aspeed: Attach GPIO device to AST1700 model
> > hw/arm/aspeed: attach I2C device to AST1700 model
> > hw/arm/aspeed: Attach WDT device to AST1700 model
> > hw/arm/aspeed: Attach PWM device to AST1700 model
> > hw/arm/aspeed: Attach SGPIOM device to AST1700 model
> > hw/arm/aspeed: Model AST1700 I3C block as unimplemented device
> > hw/arm/aspeed: Enable AST1700 IO expander support
> >
> > include/hw/arm/aspeed_ast1700.h | 53 +++++++
> > include/hw/arm/aspeed_soc.h | 25 ++-
> > include/hw/i2c/aspeed_i2c.h | 1 +
> > include/hw/intc/aspeed_intc.h | 2 +
> > include/hw/misc/aspeed_ltpi.h | 33 ++++
> > include/hw/misc/aspeed_pwm.h | 31 ++++
> > hw/arm/aspeed_ast1700.c | 268
> ++++++++++++++++++++++++++++++++
> > hw/arm/aspeed_ast27x0.c | 165 ++++++++++++++++++--
> > hw/i2c/aspeed_i2c.c | 19 ++-
> > hw/intc/aspeed_intc.c | 60 +++++++
> > hw/misc/aspeed_ltpi.c | 193 +++++++++++++++++++++++
> > hw/misc/aspeed_pwm.c | 121 ++++++++++++++
> > hw/arm/meson.build | 1 +
> > hw/misc/meson.build | 2 +
> > hw/misc/trace-events | 4 +
> > 15 files changed, 959 insertions(+), 19 deletions(-)
> > create mode 100644 include/hw/arm/aspeed_ast1700.h
> > create mode 100644 include/hw/misc/aspeed_ltpi.h
> > create mode 100644 include/hw/misc/aspeed_pwm.h
> > create mode 100644 hw/arm/aspeed_ast1700.c
> > create mode 100644 hw/misc/aspeed_ltpi.c
> > create mode 100644 hw/misc/aspeed_pwm.c
> >
^ permalink raw reply [flat|nested] 74+ messages in thread
end of thread, other threads:[~2026-01-19 7:53 UTC | newest]
Thread overview: 74+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-12-24 1:41 [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Kane Chen via
2025-12-24 1:41 ` [PATCH v4 01/19] hw/misc: Add LTPI controller Kane Chen via
2025-12-24 10:36 ` Cédric Le Goater
2025-12-29 19:37 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 02/19] hw/arm/aspeed: Attach LTPI controller to AST27X0 platform Kane Chen via
2025-12-29 19:37 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 03/19] hw/misc: Add basic Aspeed PWM model Kane Chen via
2025-12-24 10:37 ` Cédric Le Goater
2025-12-29 19:37 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 04/19] hw/arm/aspeed: Add AST1700 LTPI expander device model Kane Chen via
2025-12-24 10:38 ` Cédric Le Goater
2025-12-29 19:37 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 05/19] hw/arm/aspeed: Integrate AST1700 device into AST27X0 Kane Chen via
2025-12-29 19:37 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700 Kane Chen via
2025-12-24 10:39 ` Cédric Le Goater
2025-12-29 19:37 ` Nabih Estefan
2025-12-24 10:57 ` Cédric Le Goater
2025-12-26 1:34 ` Kane Chen
2025-12-27 17:50 ` Cédric Le Goater
2025-12-29 10:00 ` Kane Chen
2025-12-29 11:41 ` Cédric Le Goater
2025-12-29 16:51 ` Cédric Le Goater
2025-12-29 19:35 ` Nabih Estefan
2025-12-30 9:58 ` Kane Chen
2025-12-30 14:28 ` Cédric Le Goater
2025-12-31 10:15 ` Kane Chen
2025-12-31 11:49 ` Cédric Le Goater
2026-01-02 16:31 ` Cédric Le Goater
2026-01-05 9:51 ` Kane Chen
2026-01-05 11:18 ` Cédric Le Goater
2026-01-06 5:45 ` Kane Chen
2025-12-24 1:41 ` [PATCH v4 07/19] hw/arm/aspeed: Attach LTPI controller to AST1700 model Kane Chen via
2025-12-24 10:41 ` Cédric Le Goater
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 08/19] hw/arm/aspeed: Attach UART device " Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 09/19] hw/arm/aspeed: Attach SRAM " Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 10/19] hw/arm/aspeed: Attach SPI " Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 11/19] hw/arm/aspeed: Attach ADC " Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 12/19] hw/arm/aspeed: Attach SCU " Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 13/19] hw/arm/aspeed: Attach GPIO " Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 14/19] hw/arm/aspeed: attach I2C " Kane Chen via
2025-12-24 11:04 ` Cédric Le Goater
2026-01-07 14:53 ` Cédric Le Goater
2026-01-07 15:35 ` Cédric Le Goater
2026-01-08 8:53 ` Kane Chen
2026-01-08 10:24 ` Cédric Le Goater
2026-01-09 1:22 ` Jamin Lin
2026-01-09 9:02 ` Cédric Le Goater
2026-01-09 9:59 ` Kane Chen
2026-01-09 13:26 ` Cédric Le Goater
2026-01-12 8:30 ` Kane Chen
2026-01-12 8:48 ` Cédric Le Goater
2025-12-24 1:41 ` [PATCH v4 15/19] hw/arm/aspeed: Attach WDT " Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 16/19] hw/arm/aspeed: Attach PWM " Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 17/19] hw/arm/aspeed: Attach SGPIOM " Kane Chen via
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 18/19] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device Kane Chen via
2025-12-24 10:43 ` Cédric Le Goater
2025-12-29 19:38 ` Nabih Estefan
2025-12-24 1:41 ` [PATCH v4 19/19] hw/arm/aspeed: Enable AST1700 IO expander support Kane Chen via
2025-12-24 10:43 ` Cédric Le Goater
2025-12-29 19:38 ` Nabih Estefan
2025-12-29 19:37 ` [PATCH v4 00/19] hw/arm/aspeed: AST1700 LTPI support and device hookups Nabih Estefan
2026-01-19 7:45 ` Cédric Le Goater
2026-01-19 7:51 ` Kane Chen
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