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Fri, 20 Sep 2024 04:01:35 +0000 From: 0x48 Swung To: Richard Henderson , LIU Zhiwei , "qemu-devel@nongnu.org" CC: "qemu-riscv@nongnu.org" , "palmer@dabbelt.com" , "alistair.francis@wdc.com" , "dbarboza@ventanamicro.com" , "liwei1518@gmail.com" , "bmeng.cn@gmail.com" , TANG Tiancheng Subject: Re: [PATCH v4 02/12] tcg/riscv: Add basic support for vector Thread-Topic: [PATCH v4 02/12] tcg/riscv: Add basic support for vector Thread-Index: AQHbBE6HkCjgGq4WQkCpc+O+WxTXqLJS672AgAofvACAAFJBAIAACN+AgAA+ggCAAlv36A== Date: Fri, 20 Sep 2024 04:01:35 +0000 Message-ID: References: <20240911132630.461-1-zhiwei_liu@linux.alibaba.com> <20240911132630.461-3-zhiwei_liu@linux.alibaba.com> <0d591570-02c6-48c9-9e3f-ef47ac20ce7d@linaro.org> <33101e38-080d-4444-a8c3-9d01827e243f@linaro.org> <20e20fde-830f-4314-a944-e7973bda5d8c@linaro.org> In-Reply-To: <20e20fde-830f-4314-a944-e7973bda5d8c@linaro.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-reactions: allow x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SY8P300MB0282:EE_|SY8P300MB0571:EE_ x-ms-office365-filtering-correlation-id: 9b5b4a7b-79a6-4e34-d1ef-08dcd928eb61 x-microsoft-antispam: BCL:0; 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boundary="_000_SY8P300MB02825DF878585DDC68EB088CE06C2SY8P300MB0282AUSP_" MIME-Version: 1.0 X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SY8P300MB0282.AUSP300.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-Network-Message-Id: 9b5b4a7b-79a6-4e34-d1ef-08dcd928eb61 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Sep 2024 04:01:35.0379 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-rms-persistedconsumerorg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: SY8P300MB0571 Received-SPF: pass client-ip=2a01:111:f403:2818::81a; envelope-from=swung0x48@outlook.com; helo=AUS01-ME3-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 20 Sep 2024 00:44:48 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --_000_SY8P300MB02825DF878585DDC68EB088CE06C2SY8P300MB0282AUSP_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hey everyone! Late to the party. Life happens sometimes ;) Just discovered this patch and this mail list, and I'd like to provide some= background story here. I origina= lly provided my initial implementation in a downstream repo last year, name= ly https://github.com/plctlab/plct-qemu/tree/plct-riscv-backend-rvv . I'm new to contributing to qemu and also take part in the open-source commu= nity upstreaming process as a whole, so I may make mistakes in my following= claims, but I see some confusion here: 1. The PLCT branch (which includes my original commits) is open-sourced usi= ng GPLv2, which follows QEMU's upstream repo. So according to the license, = my modification should be EXPLICITLY shown in the patch, but I haven't seen= any. 2. I do consent upstreaming my patch last year, in the form of a patch subm= itted with modifications from T-head, and on behalf of them. And it was agr= eed back in the days that I can be mentioned as one of the authors. But it = turns out that there's no "sign-off", "author", "co-author" line mentioning= me. If I don't speak out in this situation, does it imply that this patch = is purely LIU Zhiwei's work and have nothing to do with me? I'd like LIU to separate my patch and his modification to two separate patc= hes, and explicitly name where are those patches coming from, so that this = patch can comply to GPLv2 license and can we clarify those misunderstanding= s. I don't want to take it personally , but I do smell something's wrong going= on here... Best Regards, Swung0x48 (aka. Huang Shiyuan) Get Outlook for Android ________________________________ From: Richard Henderson Sent: Wednesday, September 18, 2024 10:27:16 PM To: LIU Zhiwei ; qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org ; palmer@dabbelt.com ; alistair.francis@wdc.com ; dbarb= oza@ventanamicro.com ; liwei1518@gmail.com ; bmeng.cn@gmail.com ; Swung0x48 ; TANG Tiancheng Subject: Re: [PATCH v4 02/12] tcg/riscv: Add basic support for vector On 9/18/24 12:43, LIU Zhiwei wrote: > > On 2024/9/18 18:11, Richard Henderson wrote: >> On 9/18/24 07:17, LIU Zhiwei wrote: >>> >>> On 2024/9/12 2:41, Richard Henderson wrote: >>>> On 9/11/24 06:26, LIU Zhiwei wrote: >>>>> From: Swung0x48 >>>>> >>>>> The RISC-V vector instruction set utilizes the LMUL field to group >>>>> multiple registers, enabling variable-length vector registers. This >>>>> implementation uses only the first register number of each group whil= e >>>>> reserving the other register numbers within the group. >>>>> >>>>> In TCG, each VEC_IR can have 3 types (TCG_TYPE_V64/128/256), and the >>>>> host runtime needs to adjust LMUL based on the type to use different >>>>> register groups. >>>>> >>>>> This presents challenges for TCG's register allocation. Currently, we >>>>> avoid modifying the register allocation part of TCG and only expose t= he >>>>> minimum number of vector registers. >>>>> >>>>> For example, when the host vlen is 64 bits and type is TCG_TYPE_V256,= with >>>>> LMUL equal to 4, we use 4 vector registers as one register group. We = can >>>>> use a maximum of 8 register groups, but the V0 register number is res= erved >>>>> as a mask register, so we can effectively use at most 7 register grou= ps. >>>>> Moreover, when type is smaller than TCG_TYPE_V256, only 7 registers a= re >>>>> forced to be used. This is because TCG cannot yet dynamically constra= in >>>>> registers with type; likewise, when the host vlen is 128 bits and >>>>> TCG_TYPE_V256, we can use at most 15 registers. >>>>> >>>>> There is not much pressure on vector register allocation in TCG now, = so >>>>> using 7 registers is feasible and will not have a major impact on cod= e >>>>> generation. >>>>> >>>>> This patch: >>>>> 1. Reserves vector register 0 for use as a mask register. >>>>> 2. When using register groups, reserves the additional registers with= in >>>>> each group. >>>>> >>>>> Signed-off-by: TANG Tiancheng >>>>> Co-authored-by: TANG Tiancheng >>>> >>>> If there is a co-author, there should be another Signed-off-by. >>> >>> This patch has added a tag: >>> >>> Signed-off-by: TANG Tiancheng >>> >>> >>> Do you mean we should add the same tag twice? >> >> The from line is "Swung0x48 ". >> If this is an alternate email for TANG Tiancheng, > > No, Swung0x48 is another author. Then we need a proper Signed-off-by line from that author. r~ --_000_SY8P300MB02825DF878585DDC68EB088CE06C2SY8P300MB0282AUSP_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Hey everyone! Late to the party. Life ha= ppens sometimes ;)
Just discovered this patch and this mail list= , and I'd like to provide some background story here.
I originally provided m= y initial implementation in a downstream repo last year, namely https://github.com/plctlab/plct-qe= mu/tree/plct-riscv-backend-rvv .
I'm new to contributing to qemu and also take part in the= open-source community upstreaming process as a whole, so I may make mistak= es in my following claims, but I see some confusion here:
1. The PLCT branch (which includes my original commits) i= s open-sourced using GPLv2, which follows QEMU's upstream repo. So according to the license, my modification should be EXPLICITLY shown in the p= atch, but I haven't seen any.
2. I do consent upstreaming my patch last year, in = the form of a patch submitted with modifications from T-head, and on behalf= of them. And it was agreed back in the days that I can be mentioned as one= of the authors. But it turns out that there's no "sign-off", "author", "co-aut= hor" line mentioning me. If I don't speak out in this situation,= does it imply that this patch is purely LIU Zhiwei's work and have nothing= to do with me?

I'd like LIU to separate my patch= and his modification to two separate patches, and explicitly name wh= ere are those patches coming from, so that this patch can compl= y to GPLv2 license and can we clarify those misunderstandings.

I don't want to take it personally , but I do smell something's wrong going on here...

Best Regards,<= /span>
Swung0x48 (aka. Huang= Shiyuan)

From: Richard Henderson <= ;richard.henderson@linaro.org>
Sent: Wednesday, September 18, 2024 10:27:16 PM
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>; qemu-devel@nong= nu.org <qemu-devel@nongnu.org>
Cc: qemu-riscv@nongnu.org <qemu-riscv@nongnu.org>; palmer@dabb= elt.com <palmer@dabbelt.com>; alistair.francis@wdc.com <alistair.f= rancis@wdc.com>; dbarboza@ventanamicro.com <dbarboza@ventanamicro.com= >; liwei1518@gmail.com <liwei1518@gmail.com>; bmeng.cn@gmail.com <bmeng.cn@gmail.com>; Swung0x48 <swung0x48@outlook.com>; TANG = Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Subject: Re: [PATCH v4 02/12] tcg/riscv: Add basic support for vecto= r
 
On 9/18/24 12:43, LIU Zhiwei wrote:
>
> On 2024/9/18 18:11, Richard Henderson wrote:
>> On 9/18/24 07:17, LIU Zhiwei wrote:
>>>
>>> On 2024/9/12 2:41, Richard Henderson wrote:
>>>> On 9/11/24 06:26, LIU Zhiwei wrote:
>>>>> From: Swung0x48<swung0x48@outlook.com>
>>>>>
>>>>> The RISC-V vector instruction set utilizes the LMUL fi= eld to group
>>>>> multiple registers, enabling variable-length vector re= gisters. This
>>>>> implementation uses only the first register number of = each group while
>>>>> reserving the other register numbers within the group.=
>>>>>
>>>>> In TCG, each VEC_IR can have 3 types (TCG_TYPE_V64/128= /256), and the
>>>>> host runtime needs to adjust LMUL based on the type to= use different
>>>>> register groups.
>>>>>
>>>>> This presents challenges for TCG's register allocation= . Currently, we
>>>>> avoid modifying the register allocation part of TCG an= d only expose the
>>>>> minimum number of vector registers.
>>>>>
>>>>> For example, when the host vlen is 64 bits and type is= TCG_TYPE_V256, with
>>>>> LMUL equal to 4, we use 4 vector registers as one regi= ster group. We can
>>>>> use a maximum of 8 register groups, but the V0 registe= r number is reserved
>>>>> as a mask register, so we can effectively use at most = 7 register groups.
>>>>> Moreover, when type is smaller than TCG_TYPE_V256, onl= y 7 registers are
>>>>> forced to be used. This is because TCG cannot yet dyna= mically constrain
>>>>> registers with type; likewise, when the host vlen is 1= 28 bits and
>>>>> TCG_TYPE_V256, we can use at most 15 registers.
>>>>>
>>>>> There is not much pressure on vector register allocati= on in TCG now, so
>>>>> using 7 registers is feasible and will not have a majo= r impact on code
>>>>> generation.
>>>>>
>>>>> This patch:
>>>>> 1. Reserves vector register 0 for use as a mask regist= er.
>>>>> 2. When using register groups, reserves the additional= registers within
>>>>>     each group.
>>>>>
>>>>> Signed-off-by: TANG Tiancheng<tangtiancheng.ttc@ali= baba-inc.com>
>>>>> Co-authored-by: TANG Tiancheng<tangtiancheng.ttc@al= ibaba-inc.com>
>>>>
>>>> If there is a co-author, there should be another Signed-of= f-by.
>>>
>>> This patch has added a tag:
>>>
>>> Signed-off-by: TANG Tiancheng<tangtiancheng.ttc@alibaba-inc= .com>
>>>
>>>
>>> Do you mean we should add the same tag twice?
>>
>> The from line is "Swung0x48 <swung0x48@outlook.com>&quo= t;.
>> If this is an alternate email for TANG Tiancheng,
>
> No, Swung0x48 is another author.

Then we need a proper Signed-off-by line from that author.


r~
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