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Tsirkin" , Richard Henderson , Paolo Bonzini , Eric Blake , Markus Armbruster Subject: Re: [RFC 12/52] hw/acpi: Replace MachineState.smp access with topology helpers Message-ID: References: <20230213095035.158240-1-zhao1.liu@linux.intel.com> <20230213095035.158240-13-zhao1.liu@linux.intel.com> <38f00a43-dc24-0a5b-e197-536c414354e7@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <38f00a43-dc24-0a5b-e197-536c414354e7@huawei.com> Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Feb 16, 2023 at 05:31:11PM +0800, wangyanan (Y) wrote: > Date: Thu, 16 Feb 2023 17:31:11 +0800 > From: "wangyanan (Y)" > Subject: Re: [RFC 12/52] hw/acpi: Replace MachineState.smp access with > topology helpers > > Hi Zhao, > > 在 2023/2/13 17:49, Zhao Liu 写道: > > From: Zhao Liu > > > > At present, in QEMU only arm needs PPTT table to build cpu topology. > > > > Before QEMU's arm supports hybrid architectures, it's enough to limit > > the cpu topology of PPTT to smp type through the explicit smp interface > > (machine_topo_get_smp_threads()). > > > > Cc: Michael S. Tsirkin > > Cc: Igor Mammedov > > Cc: Ani Sinha > > Signed-off-by: Zhao Liu > > --- > > hw/acpi/aml-build.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c > > index ea331a20d131..693bd8833d10 100644 > > --- a/hw/acpi/aml-build.c > > +++ b/hw/acpi/aml-build.c > > @@ -2044,7 +2044,7 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, > > cluster_offset = socket_offset; > > } > > - if (ms->smp.threads == 1) { > > + if (machine_topo_get_smp_threads(ms) == 1) { > > build_processor_hierarchy_node(table_data, > > (1 << 1) | /* ACPI Processor ID valid */ > > (1 << 3), /* Node is a Leaf */ > ACPI PPTT table is designed to also support the hybrid CPU topology > case where nodes on the same CPU topology level can have different > number of child nodes. > > So to be general, the diff should be: > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c > index ea331a20d1..dfded95bbc 100644 > --- a/hw/acpi/aml-build.c > +++ b/hw/acpi/aml-build.c > @@ -2044,7 +2044,7 @@ void build_pptt(GArray *table_data, BIOSLinker > *linker, MachineState *ms, >              cluster_offset = socket_offset; >          } > > -        if (ms->smp.threads == 1) { > +        if (machine_topo_get_threads_by_idx(n) == 1) { >              build_processor_hierarchy_node(table_data, >                  (1 << 1) | /* ACPI Processor ID valid */ >                  (1 << 3),  /* Node is a Leaf */ Nice! I'll replace that. > > Actually I'm recently working on ARM hmp virtualization which relys on > PPTT for topology representation, so we will also need PPTT to be general > for hybrid case anyway. Good to know that you are considering hybrid support for arm. BTW, I explained the difference between arm and x86's hybrid in previous email [1] [2], mainly about whether the cpm model is the same. I tentatively think that this difference can be solved by arch-specific coretype(). Do you have any comments on this? Thanks! [1]: https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg03884.html [2]: https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg03789.html > > Thanks, > Yanan