From: "Dr. David Alan Gilbert" <dgilbert@redhat.com>
To: Tom Lendacky <thomas.lendacky@amd.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
"Eric Blake" <eblake@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
"Daniel P. Berrangé" <berrange@redhat.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>,
"Michael Roth" <michael.roth@amd.com>
Subject: Re: [PATCH 3/4] i386/sev: Update checks and information related to reduced-phys-bits
Date: Thu, 13 Oct 2022 14:31:12 +0100 [thread overview]
Message-ID: <Y0gTICvjTDUd8Oqw@work-vm> (raw)
In-Reply-To: <cca5341a95ac73f904e6300f10b04f9c62e4e8ff.1664550870.git.thomas.lendacky@amd.com>
* Tom Lendacky (thomas.lendacky@amd.com) wrote:
> The value of the reduced-phys-bits parameter is propogated to the CPUID
> information exposed to the guest. Update the current validation check to
> account for the size of the CPUID field (6-bits), ensuring the value is
> in the range of 1 to 63.
>
> Maintain backward compatibility, to an extent, by allowing a value greater
> than 1 (so that the previously documented value of 5 still works), but not
> allowing anything over 63.
>
> Fixes: d8575c6c02 ("sev/i386: add command to initialize the memory encryption context")
> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
> ---
> target/i386/sev.c | 17 ++++++++++++++---
> 1 file changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/target/i386/sev.c b/target/i386/sev.c
> index 32f7dbac4e..78c2d37eba 100644
> --- a/target/i386/sev.c
> +++ b/target/i386/sev.c
> @@ -932,15 +932,26 @@ int sev_kvm_init(ConfidentialGuestSupport *cgs, Error **errp)
> host_cpuid(0x8000001F, 0, NULL, &ebx, NULL, NULL);
> host_cbitpos = ebx & 0x3f;
>
> + /*
> + * The cbitpos value will be placed in bit positions 5:0 of the EBX
> + * register of CPUID 0x8000001F. No need to verify the range as the
> + * comparison against the host value accomplishes that.
> + */
> if (host_cbitpos != sev->cbitpos) {
> error_setg(errp, "%s: cbitpos check failed, host '%d' requested '%d'",
> __func__, host_cbitpos, sev->cbitpos);
> goto err;
> }
>
> - if (sev->reduced_phys_bits < 1) {
> - error_setg(errp, "%s: reduced_phys_bits check failed, it should be >=1,"
> - " requested '%d'", __func__, sev->reduced_phys_bits);
> + /*
> + * The reduced-phys-bits value will be placed in bit positions 11:6 of
> + * the EBX register of CPUID 0x8000001F, so verify the supplied value
> + * is in the range of 1 to 63.
> + */
> + if (sev->reduced_phys_bits < 1 || sev->reduced_phys_bits > 63) {
> + error_setg(errp, "%s: reduced_phys_bits check failed,"
> + " it should be in the range of 1 to 63, requested '%d'",
> + __func__, sev->reduced_phys_bits);
> goto err;
> }
>
> --
> 2.37.3
>
>
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
next prev parent reply other threads:[~2022-10-13 13:55 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-30 15:14 [PATCH 0/4] Qemu SEV reduced-phys-bits fixes Tom Lendacky
2022-09-30 15:14 ` [PATCH 1/4] qapi, i386/sev: Change the reduced-phys-bits value from 5 to 1 Tom Lendacky
2022-10-13 13:22 ` Dr. David Alan Gilbert
2022-09-30 15:14 ` [PATCH 2/4] qemu-options.hx: Update the reduced-phys-bits documentation Tom Lendacky
2022-10-13 13:29 ` Dr. David Alan Gilbert
2022-09-30 15:14 ` [PATCH 3/4] i386/sev: Update checks and information related to reduced-phys-bits Tom Lendacky
2022-10-13 13:31 ` Dr. David Alan Gilbert [this message]
2022-09-30 15:14 ` [PATCH 4/4] i386/cpu: Update how the EBX register of CPUID 0x8000001F is set Tom Lendacky
2022-10-13 14:01 ` Dr. David Alan Gilbert
2023-01-04 18:13 ` [PATCH 0/4] Qemu SEV reduced-phys-bits fixes Tom Lendacky
2023-01-09 15:05 ` Daniel P. Berrangé
2023-04-21 8:48 ` Paolo Bonzini
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