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[82.30.61.225]) by smtp.gmail.com with ESMTPSA id iv20-20020a05600c549400b003b4c40378casm5000447wmb.39.2022.10.13.06.31.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Oct 2022 06:31:14 -0700 (PDT) Date: Thu, 13 Oct 2022 14:31:12 +0100 From: "Dr. David Alan Gilbert" To: Tom Lendacky Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Eric Blake , Markus Armbruster , Daniel =?iso-8859-1?Q?P=2E_Berrang=E9?= , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Paolo Bonzini , Marcelo Tosatti , Michael Roth Subject: Re: [PATCH 3/4] i386/sev: Update checks and information related to reduced-phys-bits Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.2.7 (2022-08-07) Received-SPF: pass client-ip=170.10.129.124; envelope-from=dgilbert@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" * Tom Lendacky (thomas.lendacky@amd.com) wrote: > The value of the reduced-phys-bits parameter is propogated to the CPUID > information exposed to the guest. Update the current validation check to > account for the size of the CPUID field (6-bits), ensuring the value is > in the range of 1 to 63. > > Maintain backward compatibility, to an extent, by allowing a value greater > than 1 (so that the previously documented value of 5 still works), but not > allowing anything over 63. > > Fixes: d8575c6c02 ("sev/i386: add command to initialize the memory encryption context") > Signed-off-by: Tom Lendacky Reviewed-by: Dr. David Alan Gilbert > --- > target/i386/sev.c | 17 ++++++++++++++--- > 1 file changed, 14 insertions(+), 3 deletions(-) > > diff --git a/target/i386/sev.c b/target/i386/sev.c > index 32f7dbac4e..78c2d37eba 100644 > --- a/target/i386/sev.c > +++ b/target/i386/sev.c > @@ -932,15 +932,26 @@ int sev_kvm_init(ConfidentialGuestSupport *cgs, Error **errp) > host_cpuid(0x8000001F, 0, NULL, &ebx, NULL, NULL); > host_cbitpos = ebx & 0x3f; > > + /* > + * The cbitpos value will be placed in bit positions 5:0 of the EBX > + * register of CPUID 0x8000001F. No need to verify the range as the > + * comparison against the host value accomplishes that. > + */ > if (host_cbitpos != sev->cbitpos) { > error_setg(errp, "%s: cbitpos check failed, host '%d' requested '%d'", > __func__, host_cbitpos, sev->cbitpos); > goto err; > } > > - if (sev->reduced_phys_bits < 1) { > - error_setg(errp, "%s: reduced_phys_bits check failed, it should be >=1," > - " requested '%d'", __func__, sev->reduced_phys_bits); > + /* > + * The reduced-phys-bits value will be placed in bit positions 11:6 of > + * the EBX register of CPUID 0x8000001F, so verify the supplied value > + * is in the range of 1 to 63. > + */ > + if (sev->reduced_phys_bits < 1 || sev->reduced_phys_bits > 63) { > + error_setg(errp, "%s: reduced_phys_bits check failed," > + " it should be in the range of 1 to 63, requested '%d'", > + __func__, sev->reduced_phys_bits); > goto err; > } > > -- > 2.37.3 > > -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK